diff options
| author | V Sowmya <v.sowmya@intel.com> | 2019-04-02 18:55:15 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-04-04 10:34:28 +0000 |
| commit | e8c655dd1b2490e24640ebafb16120e5e9c268f3 (patch) | |
| tree | e9024acbbb7b60f2c5f49b58f0f302c66d9cce3c | |
| parent | c10fed07432be9fc5e4f077ca567b749a56c8f48 (diff) | |
mb/intel/coffeelake_rvp: Configure FSP UPDs of DDI ports for cmlrvp
This patch configures FSP UPD values for HPD and DDC of DDI ports for
CMLRVP.
BUG=none
TEST= Tested that eDP works on CMLRVP.
Change-Id: If8c8480eaf2d63cec0b5598b5af3088c630dd78a
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32140
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb index 6484330ae1..241ac33345 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb @@ -10,6 +10,19 @@ chip soc/intel/cannonlake register "HeciEnabled" = "1" register "s0ix_enable" = "1" + # Enable eDP device + register "DdiPortEdp" = "1" + # Enable HPD for DDI ports B/C + register "DdiPortBHpd" = "1" + register "DdiPortCHpd" = "1" + register "DdiPortDHpd" = "1" + register "DdiPortFHpd" = "1" + # Enable DDC for DDI ports B/C + register "DdiPortBDdc" = "1" + register "DdiPortCDdc" = "1" + register "DdiPortDDdc" = "1" + register "DdiPortFDdc" = "1" + register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, |