diff options
author | Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> | 2023-05-30 12:30:36 -0700 |
---|---|---|
committer | Martin L Roth <gaumless@gmail.com> | 2023-06-06 17:34:53 +0000 |
commit | e4893d6b80806b9748a3593310278e65a3f63dee (patch) | |
tree | 3cf3986b4c1b5239910f536cb1f783d9e04a8965 | |
parent | d7ad1409b955f83e40da3b648e85bc3cc2b919a8 (diff) |
soc/intel/common/crashlog: Add support for IOE die
Intel Meteor Lake SOC has a separate I/O Expander (IOE) die.
SRAM from this IOE die contains crashlog records for the IPs
of the IOE die.
This patch adds functions with empty implementation using
__weak attribute for IOE die related crashlog, changes common
data structures while maintaining backwards compatibility,
and support for filling IOE crashlog records, guarded by
SOC_INTEL_IOE_DIE_SUPPORT config and makes cl_get_pmc_sram_data
function as weak because it needs SOC specific implementation.
Bug=b:262501347
TEST=Able to build. With Meteor Lake SOC related patch, able to
capture and decode crashlog
Change-Id: Id90cf0095258c4f7003e4c5f2564bb763e687b75
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75475
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r-- | src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h | 1 | ||||
-rw-r--r-- | src/soc/intel/common/Kconfig.common | 5 | ||||
-rw-r--r-- | src/soc/intel/common/block/acpi/acpi_bert.c | 23 | ||||
-rw-r--r-- | src/soc/intel/common/block/crashlog/crashlog.c | 41 | ||||
-rw-r--r-- | src/soc/intel/common/block/include/intelblocks/crashlog.h | 47 |
5 files changed, 108 insertions, 9 deletions
diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h index 4162d84c73..5080812da4 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h @@ -39,6 +39,7 @@ #define CBMEM_ID_MPTABLE 0x534d5054 #define CBMEM_ID_MRCDATA 0x4d524344 #define CBMEM_ID_PMC_CRASHLOG 0x504d435f +#define CBMEM_ID_IOE_CRASHLOG 0x494f455f #define CBMEM_ID_VAR_MRCDATA 0x4d524345 #define CBMEM_ID_MTC 0xcb31d31c #define CBMEM_ID_NONE 0x00000000 diff --git a/src/soc/intel/common/Kconfig.common b/src/soc/intel/common/Kconfig.common index 29d1c7cff2..ed6068da54 100644 --- a/src/soc/intel/common/Kconfig.common +++ b/src/soc/intel/common/Kconfig.common @@ -149,4 +149,9 @@ config SOC_INTEL_CRASHLOG_ON_RESET This will result in a BERT table being populated containing a PMC crashlog record on every boot. +config SOC_INTEL_IOE_DIE_SUPPORT + def_bool n + help + Enable this config if the SOC support IOE DIE. + endif # SOC_INTEL_COMMON diff --git a/src/soc/intel/common/block/acpi/acpi_bert.c b/src/soc/intel/common/block/acpi/acpi_bert.c index 16df60a9d2..37309de316 100644 --- a/src/soc/intel/common/block/acpi/acpi_bert.c +++ b/src/soc/intel/common/block/acpi/acpi_bert.c @@ -87,6 +87,29 @@ static enum cb_err record_crashlog_into_bert(void **region, size_t *length) cl_fill_pmc_records(cl_data); } + if (CONFIG(SOC_INTEL_IOE_DIE_SUPPORT)) { + size_t ioe_record_size = cl_get_ioe_record_size(); + if (ioe_record_size) { + /* Allocate new FW ERR structure in case IOE crashlog is present */ + if (ioe_record_size && !bert_append_fw_err(status)) { + printk(BIOS_ERR, "Crashlog IOE entry would " + "exceed available region\n"); + return CB_ERR; + } + + cl_data = new_cper_fw_error_crashlog(status, ioe_record_size); + if (!cl_data) { + printk(BIOS_ERR, "Crashlog IOE entry(size %zu) " + "would exceed available region\n", + ioe_record_size); + return CB_ERR; + } + printk(BIOS_DEBUG, "cl_data %p, ioe_record_size %zu\n", + cl_data, ioe_record_size); + cl_fill_ioe_records(cl_data); + } + } + *length = status->data_length + gesb_header_size; *region = (void *)status; diff --git a/src/soc/intel/common/block/crashlog/crashlog.c b/src/soc/intel/common/block/crashlog/crashlog.c index 4b72599bfd..5b098bb583 100644 --- a/src/soc/intel/common/block/crashlog/crashlog.c +++ b/src/soc/intel/common/block/crashlog/crashlog.c @@ -23,6 +23,11 @@ u32 __weak cl_get_cpu_bar_addr(void) return 0; } +int __weak cl_get_ioe_record_size(void) +{ + return 0; +} + u32 __weak cl_get_cpu_tmp_bar(void) { return 0; @@ -43,6 +48,11 @@ bool __weak cl_pmc_sram_has_mmio_access(void) return false; } +bool __weak cl_ioe_sram_has_mmio_access(void) +{ + return false; +} + bool __weak cpu_crashlog_support(void) { return false; @@ -63,12 +73,19 @@ bool __weak cl_pmc_data_present(void) return false; } +bool __weak cl_ioe_data_present(void) +{ + return false; +} + __weak void reset_discovery_buffers(void) {} __weak void update_new_pmc_crashlog_size(u32 *pmc_crash_size) {} __weak void update_new_cpu_crashlog_size(u32 *cpu_crash_size) {} +__weak void update_new_ioe_crashlog_size(u32 *ioe_crash_size) {} + pmc_ipc_discovery_buf_t __weak cl_get_pmc_discovery_buf(void) { pmc_ipc_discovery_buf_t discov_buf; @@ -303,7 +320,7 @@ bool cl_copy_data_from_sram(u32 src_bar, return true; } -void cl_get_pmc_sram_data(void) +void __weak cl_get_pmc_sram_data(void) { u32 *dest = NULL; u32 tmp_bar_addr = cl_get_cpu_tmp_bar(); @@ -518,3 +535,25 @@ bool cl_fill_pmc_records(void *cl_record) return true; } + +bool cl_fill_ioe_records(void *cl_record) +{ + void *cl_src_addr = NULL; + + u32 m_ioe_crashLog_size = cl_get_ioe_record_size(); + + if (!cl_ioe_data_present() || m_ioe_crashLog_size == 0) { + printk(BIOS_DEBUG, "IOE crashLog not present, skipping.\n"); + return false; + } + + printk(BIOS_DEBUG, "IOE PMC crash data collection.\n"); + cl_src_addr = cbmem_find(CBMEM_ID_IOE_CRASHLOG); + if (!cl_src_addr) { + printk(BIOS_DEBUG, "IOE crash data, CBMEM not found\n"); + return false; + } + memcpy(cl_record, cl_src_addr, m_ioe_crashLog_size); + + return true; +} diff --git a/src/soc/intel/common/block/include/intelblocks/crashlog.h b/src/soc/intel/common/block/include/intelblocks/crashlog.h index cf9ddad553..91e8edd5a3 100644 --- a/src/soc/intel/common/block/include/intelblocks/crashlog.h +++ b/src/soc/intel/common/block/include/intelblocks/crashlog.h @@ -25,11 +25,16 @@ #define INVALID_CRASHLOG_RECORD 0xdeadbeef +/* Tag field definitions */ +#define CRASHLOG_DESCRIPTOR_TABLE_TAG_SOC 0x0 +#define CRASHLOG_DESCRIPTOR_TABLE_TAG_IOE 0x1 + /* PMC crashlog discovery structs */ typedef union { struct { - u16 offset; - u16 size; + u16 offset :16; + u16 size :13; + u16 assign_tag :3; } bits; u32 data; } __packed pmc_crashlog_discov_region_t; @@ -46,12 +51,34 @@ typedef union { u32 discov_mechanism :2; u32 size :12; u32 base_offset :16; /* Start offset of CrashLog in PMC SSRAM */ - u32 rsv :16; - u32 desc_tabl_offset :16; /* start offset of descriptor table */ + u32 rsvd :16; + u32 desc_tabl_offset :16; /* Start offset of descriptor table */ } bits; - u64 val_64_bits; -} __packed pmc_ipc_discovery_buf_t; + u64 val_64_bits; + /* Converged Capability and Status - PMC */ + struct { + /* Capability */ + u32 supported :1; /* CrashLog feature availability bit */ + u32 dis :1; /* CrashLog Disable bit */ + u32 discov_mechanism :2; /* CrashLog discovery mechanism */ + u32 manu_trig_cmd :1; /* Manuel trigger command */ + u32 clear :1; /* Clear Command */ + u32 all_reset :1; /* Trigger on all reset command */ + u32 re_arm :1; /* Re-arm command */ + u32 glb_rst_trig_mask_sup:1; /* Global reset trigger mask supported */ + u32 rsvd :18; /* Pch Specific reserved */ + /* Status */ + u32 glb_rst_trig_mask_sts :1; /* Global reset trigger mask status */ + u32 crashLog_req :1; /* CrashLog requestor flow */ + u32 trig_armed_sts :1; /* Trigger armed status */ + u32 trig_all_rst :1; /* Trigger on all resets status */ + u32 crash_dis_sts :1; /* Crash log disabled status */ + u32 pch_rsvd :16; /* Pch Specific reserved */ + u32 desc_tabl_offset :16; /* Descriptor Table offset */ + } conv_bits64; + u64 conv_val_64_bits; +} __packed pmc_ipc_discovery_buf_t; /* CPU/TELEMETRY crashlog discovery structs */ @@ -117,8 +144,7 @@ typedef union { typedef union { struct { u32 offset :32; - u32 size :16; - u32 reserved :16; + u32 size :32; } fields; u64 data; } __packed cpu_crashlog_buffer_info_t; @@ -132,20 +158,24 @@ typedef struct { int cl_get_cpu_record_size(void); int cl_get_pmc_record_size(void); +int cl_get_ioe_record_size(void); u32 cl_get_cpu_bar_addr(void); u32 cl_get_cpu_tmp_bar(void); u32 cl_get_cpu_mb_int_addr(void); int cl_get_total_data_size(void); bool cl_pmc_sram_has_mmio_access(void); +bool cl_ioe_sram_has_mmio_access(void); bool cpu_crashlog_support(void); bool pmc_crashlog_support(void); bool cl_cpu_data_present(void); bool cl_pmc_data_present(void); +bool cl_ioe_data_present(void); void cl_get_cpu_sram_data(void); void cl_get_pmc_sram_data(void); void reset_discovery_buffers(void); void update_new_pmc_crashlog_size(u32 *pmc_crash_size); void update_new_cpu_crashlog_size(u32 *cpu_crash_size); +void update_new_ioe_crashlog_size(u32 *pmc_crash_size); pmc_ipc_discovery_buf_t cl_get_pmc_discovery_buf(void); pmc_crashlog_desc_table_t cl_get_pmc_descriptor_table(void); cpu_crashlog_discovery_table_t cl_get_cpu_discovery_table(void); @@ -170,6 +200,7 @@ bool cl_copy_data_from_sram(u32 src_bar, void collect_pmc_and_cpu_crashlog_from_srams(void); bool cl_fill_cpu_records(void *cl_record); bool cl_fill_pmc_records(void *cl_record); +bool cl_fill_ioe_records(void *cl_record); static const EFI_GUID FW_ERR_SECTION_GUID = { 0x81212a96, 0x09ed, 0x4996, |