nb/intel/haswell: Put host bridge registers into its own file

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: I1d3a32a9386c0dee65eea6f9d0a2520d5e800db1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43690
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2 files changed, 69 insertions, 60 deletions

diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index baa4f32614..1255cac5d6 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -30,66 +30,7 @@
 /* Device 0:0.0 PCI configuration space (Host Bridge) */
 #define HOST_BRIDGE	PCI_DEV(0, 0, 0)
 
-#define EPBAR		0x40
-#define MCHBAR		0x48
-#define PCIEXBAR	0x60
-#define DMIBAR		0x68
-
-#define GGC		0x50			/* GMCH Graphics Control */
-#define  GGC_DISABLE_VGA_IO_DECODE	(1 << 1)
-#define  GGC_IGD_MEM_IN_32MB_UNITS(x)	(((x) & 0x1f) << 3)
-#define  GGC_GTT_0MB			(0 << 8)
-#define  GGC_GTT_1MB			(1 << 8)
-#define  GGC_GTT_2MB			(2 << 8)
-
-#define DEVEN		0x54			/* Device Enable */
-#define  DEVEN_D7EN	(1 << 14)
-#define  DEVEN_D4EN	(1 << 7)
-#define  DEVEN_D3EN	(1 << 5)
-#define  DEVEN_D2EN	(1 << 4)
-#define  DEVEN_D1F0EN	(1 << 3)
-#define  DEVEN_D1F1EN	(1 << 2)
-#define  DEVEN_D1F2EN	(1 << 1)
-#define  DEVEN_D0EN	(1 << 0)
-
-#define PAM0		0x80
-#define PAM1		0x81
-#define PAM2		0x82
-#define PAM3		0x83
-#define PAM4		0x84
-#define PAM5		0x85
-#define PAM6		0x86
-
-#define LAC		0x87	/* Legacy Access Control */
-#define SMRAM		0x88	/* System Management RAM Control */
-#define  D_OPEN		(1 << 6)
-#define  D_CLS		(1 << 5)
-#define  D_LCK		(1 << 4)
-#define  G_SMRAME	(1 << 3)
-#define  C_BASE_SEG	((0 << 2) | (1 << 1) | (0 << 0))
-
-#define MESEG_BASE	0x70	/* Management Engine Base */
-#define MESEG_LIMIT	0x78	/* Management Engine Limit */
-#define REMAPBASE	0x90	/* Remap base */
-#define REMAPLIMIT	0x98	/* Remap limit */
-#define TOM		0xa0	/* Top of DRAM in memory controller space */
-#define TOUUD		0xa8	/* Top of Upper Usable DRAM */
-#define BDSM		0xb0	/* Base Data Stolen Memory */
-#define BGSM		0xb4	/* Base GTT Stolen Memory */
-#define TSEG		0xb8	/* TSEG base */
-#define TOLUD		0xbc	/* Top of Low Used Memory */
-
-#define SKPAD		0xdc	/* Scratchpad Data */
-
-#define CAPID0_A	0xe4
-#define  VTD_DISABLE	(1 << 23)
-#define ARCHDIS		0xff0	/* DMA Remap Engine Policy Control */
-#define  DMAR_LCKDN	(1 << 31)
-#define  SPCAPCTRL	(1 << 25)
-#define  L3HIT2PEND_DIS	(1 << 20)
-#define  PRSCAPDIS	(1 << 2)
-#define  GLBIOTLBINV	(1 << 1)
-#define  GLBCTXTINV	(1 << 0)
+#include "hostbridge_regs.h"
 
 
 /* Device 0:2.0 PCI configuration space (Graphics Device) */
@@ -116,6 +57,14 @@
 /* As there are many registers, define them on a separate file */
 #include "mchbar_regs.h"
 
+#define ARCHDIS		0xff0	/* DMA Remap Engine Policy Control */
+#define  DMAR_LCKDN	(1 << 31)
+#define  SPCAPCTRL	(1 << 25)
+#define  L3HIT2PEND_DIS	(1 << 20)
+#define  PRSCAPDIS	(1 << 2)
+#define  GLBIOTLBINV	(1 << 1)
+#define  GLBCTXTINV	(1 << 0)
+
 /*
  * EPBAR - Egress Port Root Complex Register Block
  */
diff --git a/src/northbridge/intel/haswell/hostbridge_regs.h b/src/northbridge/intel/haswell/hostbridge_regs.h
new file mode 100644
index 0000000000..b462a09a69
--- /dev/null
+++ b/src/northbridge/intel/haswell/hostbridge_regs.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __HASWELL_HOSTBRIDGE_REGS_H__
+#define __HASWELL_HOSTBRIDGE_REGS_H__
+
+#define EPBAR		0x40
+#define MCHBAR		0x48
+#define PCIEXBAR	0x60
+#define DMIBAR		0x68
+
+#define GGC		0x50			/* GMCH Graphics Control */
+#define  GGC_DISABLE_VGA_IO_DECODE	(1 << 1)
+#define  GGC_IGD_MEM_IN_32MB_UNITS(x)	(((x) & 0x1f) << 3)
+#define  GGC_GTT_0MB			(0 << 8)
+#define  GGC_GTT_1MB			(1 << 8)
+#define  GGC_GTT_2MB			(2 << 8)
+
+#define DEVEN		0x54			/* Device Enable */
+#define  DEVEN_D7EN	(1 << 14)
+#define  DEVEN_D4EN	(1 << 7)
+#define  DEVEN_D3EN	(1 << 5)
+#define  DEVEN_D2EN	(1 << 4)
+#define  DEVEN_D1F0EN	(1 << 3)
+#define  DEVEN_D1F1EN	(1 << 2)
+#define  DEVEN_D1F2EN	(1 << 1)
+#define  DEVEN_D0EN	(1 << 0)
+
+#define PAM0		0x80
+#define PAM1		0x81
+#define PAM2		0x82
+#define PAM3		0x83
+#define PAM4		0x84
+#define PAM5		0x85
+#define PAM6		0x86
+
+#define LAC		0x87	/* Legacy Access Control */
+#define SMRAM		0x88	/* System Management RAM Control */
+#define  D_OPEN		(1 << 6)
+#define  D_CLS		(1 << 5)
+#define  D_LCK		(1 << 4)
+#define  G_SMRAME	(1 << 3)
+#define  C_BASE_SEG	((0 << 2) | (1 << 1) | (0 << 0))
+
+#define MESEG_BASE	0x70	/* Management Engine Base */
+#define MESEG_LIMIT	0x78	/* Management Engine Limit */
+#define REMAPBASE	0x90	/* Remap base */
+#define REMAPLIMIT	0x98	/* Remap limit */
+#define TOM		0xa0	/* Top of DRAM in memory controller space */
+#define TOUUD		0xa8	/* Top of Upper Usable DRAM */
+#define BDSM		0xb0	/* Base Data Stolen Memory */
+#define BGSM		0xb4	/* Base GTT Stolen Memory */
+#define TSEG		0xb8	/* TSEG base */
+#define TOLUD		0xbc	/* Top of Low Used Memory */
+
+#define SKPAD		0xdc	/* Scratchpad Data */
+
+#define CAPID0_A	0xe4
+#define  VTD_DISABLE	(1 << 23)
+
+#endif /* __HASWELL_HOSTBRIDGE_REGS_H__ */