diff options
| author | Sean Rhodes <sean@starlabs.systems> | 2023-03-27 10:59:02 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-04-04 14:09:19 +0000 |
| commit | db8ef01e300943fb9bd08c0f988d91c6cc326616 (patch) | |
| tree | debd1317664c1049918c82abc2382a324861b51a | |
| parent | 7d6ae2b72c0a4b521d2492fab606e1544f72e979 (diff) | |
mb/starlabs/starbook: Disable ASPM in coreboot
ASPM is already configured by FSP so disable it in coreboot to
reduce boot time by a whopping 34ms.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I073c68dafa9baa90e253b5230f84b0de6a7e5c47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73982
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
| -rw-r--r-- | src/mainboard/starlabs/starbook/Kconfig | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig index d35a4d270f..b2dfe12971 100644 --- a/src/mainboard/starlabs/starbook/Kconfig +++ b/src/mainboard/starlabs/starbook/Kconfig @@ -145,9 +145,30 @@ config EDK2_BOOTSPLASH_FILE string default "3rdparty/blobs/mainboard/starlabs/Logo.bmp" +config PCIEXP_ASPM + bool + default n + help + FSP is already taking care of ASPM, which is configured through the devicetree in coreboot + on Alderlake Platforms. Disable it to save some boot time. + config PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS default 32 +config PCIEXP_L1_SUB_STATE + bool + default n + help + Enabling PCIe L1 sub states is already done in FSP. + Disable it to save some boot time. + +config PCIEXP_CLK_PM + bool + default n + help + Enabling PCIe clock power management is already done in FSP. + Disable it to save some boot time + config SOC_INTEL_CSE_SEND_EOP_EARLY default n if BOARD_STARLABS_STARBOOK_ADL |