diff options
| author | Tim Van Patten <timvp@google.com> | 2022-09-15 17:21:38 -0600 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2022-09-19 09:57:12 +0000 |
| commit | d8210d6ee12aa07e6a04bc861a56a9d099180226 (patch) | |
| tree | e61ce69abe9259e0a342b1129c448b334e83112e | |
| parent | 7a6451bd3e0332b6629d7b53696bfa88ffb42303 (diff) | |
amd/mendocino/acpi/soc: Add DPTC Support
Add support for DPTC by calling SB.DPTC() as part of PNOT().
BRANCH=none
BUG=b:217911928
TEST=Boot skyrim
Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: Ifc332bfc4d273031c93b77673224b4f3c2871fb1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67694
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/amd/mendocino/acpi/soc.asl | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/amd/mendocino/acpi/soc.asl b/src/soc/amd/mendocino/acpi/soc.asl index 91b1444c1d..5af6d8c533 100644 --- a/src/soc/amd/mendocino/acpi/soc.asl +++ b/src/soc/amd/mendocino/acpi/soc.asl @@ -35,6 +35,9 @@ Scope(\_SB) { #include "rtc_workaround.asl" +/* Enable DPTC interface with AMD ALIB */ +External(\_SB.DPTC, MethodObj) + /* * Platform Notify * @@ -44,4 +47,8 @@ Method (PNOT) { /* Report AC/DC state to ALIB using WAL1() */ \WAL1 () + + If (CondRefOf (\_SB.DPTC)) { + \_SB.DPTC() + } } |