diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-06-16 21:14:25 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-06-20 18:43:30 +0200 |
| commit | d71cfd204109b66aef0fe233e1e78e3c840fed6d (patch) | |
| tree | 39ad85048b7defc516d7c8548c24166266906d1a | |
| parent | 4b86314495b17f8d944e16cfb726cd665c7d22a1 (diff) | |
VIA C7 NANO: Fix early MTRR setting
It would not be possible to set MTRR for range 1MiB to 4MiB.
Our RAMTOP is power of 2 and enabling cache for bottom
1MiB should cause no problems.
Change-Id: I3619bc25be60f42b68615bfcdf36f02d66796e02
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15238
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| -rw-r--r-- | src/cpu/via/car/cache_as_ram.inc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index 046d9c46d5..2f61b9138a 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -225,15 +225,15 @@ testok: movl $(MTRR_DEF_TYPE_EN), %eax wrmsr - /* Enable caching for CONFIG_RAMBASE..CONFIG_RAMTOP. */ + /* Enable caching for 0..CONFIG_RAMTOP. */ movl $MTRR_PHYS_BASE(0), %ecx xorl %edx, %edx - movl $(CONFIG_RAMBASE | MTRR_TYPE_WRBACK), %eax + movl $(0x0 | MTRR_TYPE_WRBACK), %eax wrmsr movl $MTRR_PHYS_MASK(0), %ecx movl $0x0000000f, %edx /* AMD 40 bit 0xff */ - movl $(~(CONFIG_RAMTOP - CONFIG_RAMBASE - 1) | MTRR_PHYS_MASK_VALID), %eax + movl $(~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax wrmsr /* Cache XIP_ROM area to speedup coreboot code. */ |