diff options
| author | Werner Zeh <werner.zeh@siemens.com> | 2021-10-22 10:59:41 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-11-02 08:14:05 +0000 |
| commit | d6798e96fcb3206ba68ee49173356ab2bd032eeb (patch) | |
| tree | ff929357953ee259436887768f34c418ead263d1 | |
| parent | fec936659ccb880278bd67fa154897a5b223f7cc (diff) | |
mb/siemens/mc_ehl1: Clean up PCIe root port settings in devicetree
PCIe root ports #5 (00:1c.4) and #6 (00:1c.5) are not used on this
mainboard and are not routed either, so remove them from the devicetree
completely. PCIe root port #7 (00:1c.6) is connected and used. Add the
missing settings for L1 substates and latency reporting to disable these
features for this port as well.
Change-Id: I06f59f0369ffcd958b5fe12bb3c646d37103811f
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58568
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb | 10 |
1 files changed, 2 insertions, 8 deletions
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb index 49fd515199..f6ac8b705f 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb @@ -51,8 +51,6 @@ chip soc/intel/elkhartlake register "PcieRpEnable[1]" = "1" register "PcieRpEnable[2]" = "1" register "PcieRpEnable[3]" = "1" - register "PcieRpEnable[4]" = "1" - register "PcieRpEnable[5]" = "1" register "PcieRpEnable[6]" = "1" register "PcieClkSrcUsage[0]" = "0x00" @@ -74,16 +72,14 @@ chip soc/intel/elkhartlake register "PcieRpL1Substates[1]" = "L1_SS_DISABLED" register "PcieRpL1Substates[2]" = "L1_SS_DISABLED" register "PcieRpL1Substates[3]" = "L1_SS_DISABLED" - register "PcieRpL1Substates[4]" = "L1_SS_DISABLED" - register "PcieRpL1Substates[5]" = "L1_SS_DISABLED" + register "PcieRpL1Substates[6]" = "L1_SS_DISABLED" # Disable LTR for all PCIe root ports register "PcieRpLtrDisable[0]" = "true" register "PcieRpLtrDisable[1]" = "true" register "PcieRpLtrDisable[2]" = "true" register "PcieRpLtrDisable[3]" = "true" - register "PcieRpLtrDisable[4]" = "true" - register "PcieRpLtrDisable[5]" = "true" + register "PcieRpLtrDisable[6]" = "true" # Storage (SATA/SDCARD/EMMC) related UPDs register "SataSalpSupport" = "0" @@ -157,8 +153,6 @@ chip soc/intel/elkhartlake device pci 1c.1 on end # RP2 (pcie0 single VC) device pci 1c.2 on end # RP3 (pcie0 single VC) device pci 1c.3 on end # RP4 (pcie0 single VC) - device pci 1c.4 on end # RP5 (pcie1 multi VC) - device pci 1c.5 on end # RP6 (pcie2 multi VC) device pci 1c.6 on end # RP7 (pcie3 multi VC) device pci 1e.0 on end # UART0 |