diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2021-07-16 20:51:08 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-07-17 21:32:59 +0000 |
| commit | d5b51beb797700f83f6d894e83679739280d8f11 (patch) | |
| tree | 9671ba734218f26227355c477b3204ff34ea1727 | |
| parent | 81d367feee138798f57ec1217209cb1c28244daa (diff) | |
soc/amd/cezanne/graphics: add VBIOS ID remapping for Barcelo
Barcelo uses the same VBIOS image as Cezanne, but uses a different PCI
ID, so we need to implement map_oprom_vendev for the SoC.
BUG=b:193888172
Change-Id: I2eed43705f497245bd953659844b3fb461aa0b3b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56392
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/amd/cezanne/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/graphics.c | 19 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/include/soc/cpu.h | 3 |
3 files changed, 23 insertions, 1 deletions
diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 478eeccac3..d693ec6576 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -33,7 +33,6 @@ romstage-y += uart.c ramstage-y += i2c.c ramstage-y += acpi.c ramstage-y += cppc.c - ramstage-y += agesa_acpi.c ramstage-y += chip.c ramstage-y += cpu.c @@ -41,6 +40,7 @@ ramstage-y += data_fabric.c ramstage-y += fch.c ramstage-y += fsp_s_params.c ramstage-y += gpio.c +ramstage-y += graphics.c ramstage-y += mca.c ramstage-y += reset.c ramstage-y += root_complex.c diff --git a/src/soc/amd/cezanne/graphics.c b/src/soc/amd/cezanne/graphics.c new file mode 100644 index 0000000000..491ca871f0 --- /dev/null +++ b/src/soc/amd/cezanne/graphics.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pci_rom.h> +#include <soc/cpu.h> +#include <stdint.h> + +u32 map_oprom_vendev(u32 vendev) +{ + u32 new_vendev = vendev; + + switch (vendev) { + case CEZANNE_VBIOS_VID_DID: + case BARCELO_VBIOS_VID_DID: + new_vendev = CEZANNE_VBIOS_VID_DID; + break; + } + + return new_vendev; +} diff --git a/src/soc/amd/cezanne/include/soc/cpu.h b/src/soc/amd/cezanne/include/soc/cpu.h index 27647adbd1..926fd05de7 100644 --- a/src/soc/amd/cezanne/include/soc/cpu.h +++ b/src/soc/amd/cezanne/include/soc/cpu.h @@ -5,4 +5,7 @@ #define CEZANNE_A0_CPUID 0x00a50f00 +#define CEZANNE_VBIOS_VID_DID 0x10021638 +#define BARCELO_VBIOS_VID_DID 0x100215e7 + #endif /* AMD_CEZANNE_CPU_H */ |