soc/intel/xeon_sp/spr: Drop devicetree setting X2apic

Drop devicetree setting X2apic as the same functionality is already
exposed in Kconfig.

To activate X2apic select X2APIC_ONLY or X2APIC_RUNTIME in
the "APIC operation mode".

Note: Your OS must have support for X2APIC. If you are using less
      than 256 CPU cores select XAPIC_ONLY here.

Test:
- Booted to OS in X2APIC mode when X2APIC_ONLY or X2APIC_RUNTIME
  was selected.
- Booted to OS in XAPIC mode when XAPIC_ONLY was selected.

Change-Id: I65152b0696a45b62a5629fd95801187354c7a93b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

2 files changed, 6 insertions, 6 deletions

diff --git a/src/soc/intel/xeon_sp/spr/chip.h b/src/soc/intel/xeon_sp/spr/chip.h
index 5144372ce6..28af550e3a 100644
--- a/src/soc/intel/xeon_sp/spr/chip.h
+++ b/src/soc/intel/xeon_sp/spr/chip.h
@@ -46,7 +46,6 @@ struct soc_intel_xeon_sp_spr_config {
 	uint32_t pstate_req_ratio;
 
 	uint8_t vtd_support;
-	uint8_t x2apic;
 
 	/* Generic IO decode ranges */
 	uint32_t gen1_dec;
diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c
index f4eae9c4a9..aacc3ab813 100644
--- a/src/soc/intel/xeon_sp/spr/romstage.c
+++ b/src/soc/intel/xeon_sp/spr/romstage.c
@@ -159,11 +159,12 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 
 	m_cfg->BoardTypeBitmask = 0x11111133;
 
-	m_cfg->X2apic = config->x2apic;
-
-	printk(BIOS_INFO, "m_cfg->X2apic = 0x%x  config->x2apic = 0x%x\n", m_cfg->X2apic,
-	       config->x2apic);
-
+	/*
+	 * Let coreboot configure LAPIC based on Kconfig.
+	 * coreboot currently can only switch from XAPIC to X2APIC,
+	 * so always select XAPIC mode here.
+	 */
+	m_cfg->X2apic = 0;
 
 	m_cfg->serialDebugMsgLvl = 0x3;