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authorKevin Chiu <kevin.chiu.17802@gmail.com>2022-12-01 19:58:59 +0800
committerNick Vaccaro <nvaccaro@google.com>2022-12-08 16:59:14 +0000
commitcc846838b6cd512a34ba8c872ee95c2dd5499e87 (patch)
treec0bb4e83e795844033ee7db15302c623f46ccbd4
parentfd39a8ef1f6b1b8b0910136b6eaef909890d0072 (diff)
mb/google/brya/var/gladios: Update fw_config STORAGE field
option STORAGE_EMMC 0 option STORAGE_NVME 1 BUG=b:239513596 TEST=FW_NAME=gladios emerge-brask coreboot Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: I27baa2ca8c2b334fb81aa87b22c3b7c028c38cd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70223 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricky Chang <rickytlchang@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
-rw-r--r--src/mainboard/google/brya/variants/gladios/overridetree.cb11
1 files changed, 10 insertions, 1 deletions
diff --git a/src/mainboard/google/brya/variants/gladios/overridetree.cb b/src/mainboard/google/brya/variants/gladios/overridetree.cb
index ae099c33c1..c8e3da5ab1 100644
--- a/src/mainboard/google/brya/variants/gladios/overridetree.cb
+++ b/src/mainboard/google/brya/variants/gladios/overridetree.cb
@@ -1,3 +1,10 @@
+fw_config
+ field STORAGE 1 1
+ option STORAGE_EMMC 0
+ option STORAGE_NVME 1
+ end
+end
+
chip soc/intel/alderlake
register "sagv" = "SaGv_Enabled"
@@ -142,7 +149,8 @@ chip soc/intel/alderlake
.clk_src = 0,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
- end
+ probe STORAGE STORAGE_NVME
+ end #NVMe
device ref tbt_pcie_rp0 off end
device ref tbt_pcie_rp1 off end
device ref tbt_pcie_rp2 off end
@@ -201,6 +209,7 @@ chip soc/intel/alderlake
.clk_req = 4,
.flags = PCIE_RP_HOTPLUG | PCIE_RP_AER,
}"
+ probe STORAGE STORAGE_EMMC
end #PCIE12 EMMC
device ref gspi1 off end
device ref pch_espi on