diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-10-11 14:26:42 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-10-15 13:43:05 +0000 |
| commit | cb70d836ed048b81ad8047e97c9758680cc2da2d (patch) | |
| tree | 3b94940d19c31ddb080ac9cce30cae9be3016ea8 | |
| parent | adb393bdd6cd6734fa2672bd174aca4588a68016 (diff) | |
cpu/intel/haswell: Lock PKG_CST_CONFIG_CONTROL MSR
Set PKG_CST_CONFIG_CONTROL MSR bit 15 to make bits 15:0 read-only.
Change-Id: Ieb740aa94255cb3c23a56495c4b645d847637b7f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
| -rw-r--r-- | src/cpu/intel/haswell/haswell_init.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 2c6384c4e3..90db95b8df 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -395,6 +395,7 @@ static void configure_c_states(void) msr.lo |= (1 << 27); // C3 Auto Undemotion Enable msr.lo |= (1 << 26); // C1 Auto Demotion Enable msr.lo |= (1 << 25); // C3 Auto Demotion Enable + msr.lo |= (1 << 15); // Lock bits 15:0 msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection if (timed_mwait_capable) |