nb/intel/haswell: Use <device/dram/ddr3.h>

Change-Id: I353ceb7ab5ec0c82f5e717c856ad7934fcbd03b6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82355
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

5 files changed, 20 insertions, 19 deletions

diff --git a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c
index 7af21f578a..0bb6f28a6a 100644
--- a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c
+++ b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c
@@ -8,6 +8,7 @@
 #include <cbmem.h>
 #include <cbfs.h>
 #include <cf9_reset.h>
+#include <device/dram/ddr3.h>
 #include <memory_info.h>
 #include <mrc_cache.h>
 #include <device/device.h>
@@ -245,7 +246,6 @@ static void setup_sdram_meminfo(struct pei_data *pei_data)
 }
 
 #include <device/smbus_host.h>
-#define SPD_LEN 256
 
 /* Copy SPD data for on-board memory */
 static void copy_spd(struct pei_data *pei_data, struct spd_info *spdi)
@@ -261,20 +261,21 @@ static void copy_spd(struct pei_data *pei_data, struct spd_info *spdi)
 	if (!spd_file)
 		die("SPD data not found.");
 
-	if (spd_file_len < ((spdi->spd_index + 1) * SPD_LEN)) {
+	if (spd_file_len < ((spdi->spd_index + 1) * SPD_SIZE_MAX_DDR3)) {
 		printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
 		spdi->spd_index = 0;
 	}
 
-	if (spd_file_len < SPD_LEN)
+	if (spd_file_len < SPD_SIZE_MAX_DDR3)
 		die("Missing SPD data.");
 
 	/* MRC only uses index 0, but coreboot uses the other indices */
-	memcpy(pei_data->spd_data[0], spd_file + (spdi->spd_index * SPD_LEN), SPD_LEN);
+	memcpy(pei_data->spd_data[0], spd_file + (spdi->spd_index * SPD_SIZE_MAX_DDR3),
+		SPD_SIZE_MAX_DDR3);
 
 	for (size_t i = 1; i < ARRAY_SIZE(spdi->addresses); i++) {
 		if (spdi->addresses[i] == SPD_MEMORY_DOWN)
-			memcpy(pei_data->spd_data[i], pei_data->spd_data[0], SPD_LEN);
+			memcpy(pei_data->spd_data[i], pei_data->spd_data[0], SPD_SIZE_MAX_DDR3);
 	}
 }
 
diff --git a/src/northbridge/intel/haswell/haswell_mrc/pei_data.h b/src/northbridge/intel/haswell/haswell_mrc/pei_data.h
index c455e17d45..c8b2e2217a 100644
--- a/src/northbridge/intel/haswell/haswell_mrc/pei_data.h
+++ b/src/northbridge/intel/haswell/haswell_mrc/pei_data.h
@@ -8,8 +8,6 @@
 typedef void (*tx_byte_func)(unsigned char byte);
 #define PEI_VERSION 15
 
-#define SPD_LEN 256
-
 #define PEI_USB_OC_PIN_SKIP 8
 
 enum pei_usb2_port_location {
@@ -82,7 +80,7 @@ struct pei_data
 	int usb_xhci_on_resume;
 	struct pei_usb2_port_setting usb2_ports[16];
 	struct pei_usb3_port_setting usb3_ports[16];
-	uint8_t spd_data[4][SPD_LEN];
+	uint8_t spd_data[4][SPD_SIZE_MAX_DDR3];
 	tx_byte_func tx_byte;
 } __packed;
 
diff --git a/src/northbridge/intel/haswell/haswell_mrc/raminit.c b/src/northbridge/intel/haswell/haswell_mrc/raminit.c
index d97ab2a8ac..52bb3b1d65 100644
--- a/src/northbridge/intel/haswell/haswell_mrc/raminit.c
+++ b/src/northbridge/intel/haswell/haswell_mrc/raminit.c
@@ -291,20 +291,21 @@ static void copy_spd(struct pei_data *pei_data, struct spd_info *spdi)
 	if (!spd_file)
 		die("SPD data not found.");
 
-	if (spd_file_len < ((spdi->spd_index + 1) * SPD_LEN)) {
+	if (spd_file_len < ((spdi->spd_index + 1) * SPD_SIZE_MAX_DDR3)) {
 		printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
 		spdi->spd_index = 0;
 	}
 
-	if (spd_file_len < SPD_LEN)
+	if (spd_file_len < SPD_SIZE_MAX_DDR3)
 		die("Missing SPD data.");
 
 	/* MRC only uses index 0, but coreboot uses the other indices */
-	memcpy(pei_data->spd_data[0], spd_file + (spdi->spd_index * SPD_LEN), SPD_LEN);
+	memcpy(pei_data->spd_data[0], spd_file + (spdi->spd_index * SPD_SIZE_MAX_DDR3),
+		SPD_SIZE_MAX_DDR3);
 
 	for (size_t i = 1; i < ARRAY_SIZE(spdi->addresses); i++) {
 		if (spdi->addresses[i] == SPD_MEMORY_DOWN)
-			memcpy(pei_data->spd_data[i], pei_data->spd_data[0], SPD_LEN);
+			memcpy(pei_data->spd_data[i], pei_data->spd_data[0], SPD_SIZE_MAX_DDR3);
 	}
 }
 
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
index 2a168666ac..8078c9c386 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
@@ -6,7 +6,8 @@
 #include <device/dram/ddr3.h>
 #include <northbridge/intel/haswell/haswell.h>
 
-#define SPD_LEN 256
+/** TODO (Angel): Remove this after in-review patches are submitted **/
+#define SPD_LEN SPD_SIZE_MAX_DDR3
 
 /* 8 data lanes + 1 ECC lane */
 #define NUM_LANES		9
diff --git a/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c b/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c
index 2dab8504c4..eff993800b 100644
--- a/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c
+++ b/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c
@@ -27,24 +27,24 @@ static const uint8_t *get_spd_data_from_cbfs(struct spd_info *spdi)
 		return NULL;
 	}
 
-	if (spd_file_len < ((spdi->spd_index + 1) * SPD_LEN)) {
+	if (spd_file_len < ((spdi->spd_index + 1) * SPD_SIZE_MAX_DDR3)) {
 		printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
 		spdi->spd_index = 0;
 	}
 
-	if (spd_file_len < SPD_LEN) {
+	if (spd_file_len < SPD_SIZE_MAX_DDR3) {
 		printk(BIOS_ERR, "Invalid SPD data in CBFS\n");
 		return NULL;
 	}
 
-	return spd_file + (spdi->spd_index * SPD_LEN);
+	return spd_file + (spdi->spd_index * SPD_SIZE_MAX_DDR3);
 }
 
 static void get_spd_for_dimm(struct raminit_dimm_info *const dimm, const uint8_t *cbfs_spd)
 {
 	if (dimm->spd_addr == SPD_MEMORY_DOWN) {
 		if (cbfs_spd) {
-			memcpy(dimm->raw_spd, cbfs_spd, SPD_LEN);
+			memcpy(dimm->raw_spd, cbfs_spd, SPD_SIZE_MAX_DDR3);
 			dimm->valid = true;
 			printk(RAM_DEBUG, "memory-down\n");
 			return;
@@ -60,9 +60,9 @@ static void get_spd_for_dimm(struct raminit_dimm_info *const dimm, const uint8_t
 		return;
 	}
 	printk(RAM_DEBUG, "and DDR3\n");
-	if (i2c_eeprom_read(dimm->spd_addr, 0, SPD_LEN, dimm->raw_spd) != SPD_LEN) {
+	if (i2c_eeprom_read(dimm->spd_addr, 0, SPD_SIZE_MAX_DDR3, dimm->raw_spd) != SPD_SIZE_MAX_DDR3) {
 		printk(BIOS_WARNING, "I2C block read failed, trying SMBus byte reads\n");
-		for (uint32_t i = 0; i < SPD_LEN; i++)
+		for (uint32_t i = 0; i < SPD_SIZE_MAX_DDR3; i++)
 			dimm->raw_spd[i] = smbus_read_byte(dimm->spd_addr, i);
 	}
 	dimm->valid = true;