diff options
| author | Matt Papageorge <matthewpapa07@gmail.com> | 2021-05-14 14:08:53 -0500 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-08-23 14:06:32 +0000 |
| commit | c8f926addac7f2bf8ea8836a31337430aa63db9f (patch) | |
| tree | ade01e39d164eaf9221cd4c4a406787adc5e32fe | |
| parent | 77fb9a0bb245acaa334cde2b4c72ff4dcf58f379 (diff) | |
mb/google/guybrush: Enable PCIe L1 Substates
This change enables L1.1 and L1.2 on all real Guybrush PCIe devices.
BUG=b:188123142
TEST=Boot to ChromeOS and verify L1SS are functional by dumping the
settings with "lspci -vv". Leave system on for 20 minutes and no hang.
Also perform 20 reboots and suspend operations
Cq-Depend: chrome-internal:4012927
Change-Id: I40d19be78bfcb9a30fb59f48530a4413dadbefbc
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
| -rw-r--r-- | src/mainboard/google/guybrush/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/google/guybrush/port_descriptors.c | 8 |
2 files changed, 9 insertions, 0 deletions
diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig index 2da9230970..d4c54a5159 100644 --- a/src/mainboard/google/guybrush/Kconfig +++ b/src/mainboard/google/guybrush/Kconfig @@ -37,6 +37,7 @@ config BOARD_SPECIFIC_OPTIONS select PCIEXP_ASPM select PCIEXP_CLK_PM select PCIEXP_COMMON_CLOCK + select PCIEXP_L1_SUB_STATE select PSP_DISABLE_POSTCODES select SOC_AMD_CEZANNE select SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF diff --git a/src/mainboard/google/guybrush/port_descriptors.c b/src/mainboard/google/guybrush/port_descriptors.c index a83db6cd1f..e1c78da449 100644 --- a/src/mainboard/google/guybrush/port_descriptors.c +++ b/src/mainboard/google/guybrush/port_descriptors.c @@ -16,6 +16,8 @@ static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = { .device_number = PCI_SLOT(WLAN_DEVFN), .function_number = PCI_FUNC(WLAN_DEVFN), .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, .clk_req = CLK_REQ0, .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} @@ -28,6 +30,8 @@ static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = { .device_number = PCI_SLOT(SD_DEVFN), .function_number = PCI_FUNC(SD_DEVFN), .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, .clk_req = CLK_REQ1, .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} @@ -40,6 +44,8 @@ static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = { .device_number = PCI_SLOT(WWAN_DEVFN), .function_number = PCI_FUNC(WWAN_DEVFN), .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, .clk_req = CLK_REQ2, .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} @@ -52,6 +58,8 @@ static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = { .device_number = PCI_SLOT(NVME_DEVFN), .function_number = PCI_FUNC(NVME_DEVFN), .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, .clk_req = CLK_REQ3, .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} |