diff options
| author | Matt DeVillier <matt.devillier@amd.corp-partner.google.com> | 2022-11-03 16:16:25 -0500 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-11-07 14:17:00 +0000 |
| commit | c848ff6eb7cca53a3afa89e37d05c6398cf5d2e5 (patch) | |
| tree | 6ca873a4bbf8fa5b1c2f4418e1692eb6ede69f88 | |
| parent | 65a0e5a92def54a505a2053b57e96d3b4dfe5289 (diff) | |
mb/google/guybrush: Implement touchscreen power sequencing
As all variants have a touchscreen option, in baseboard table set the
enable GPIO high and hold in reset during romstage, then release reset
in ramstage. This will allow the touchscreen to make use of the runtime
I2C detect feature (enabled in a subsequent commit) so that an ACPI
device entry is created only for the touchscreen actually present.
Variants/SKUs which do not have a touchscreen (if any) can use the
romstage/ramstage GPIO override tables to set the associated enable/
reset GPIOs to NC.
This mirrors the change to skyrim in CB:67778.
BUG=b:121309055
TEST=build/boot guybrush with rest of patch series
Change-Id: I9b3356b8b3a0e68a307838a4b18775d25b32e548
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
| -rw-r--r-- | src/mainboard/google/guybrush/variants/baseboard/gpio.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c index beb654f013..595f680487 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c @@ -135,7 +135,7 @@ static const struct soc_amd_gpio base_gpio_table[] = { /* TCHSCR_REPORT_EN */ PAD_GPO(GPIO_120, LOW), /* TCHSCR_RESET_L */ - PAD_GPO(GPIO_121, LOW), + PAD_GPO(GPIO_121, HIGH), /* GPIO_122 - GPIO_128: Not available */ /* SOC_DISABLE_DISP_BL */ PAD_GPO(GPIO_129, LOW), @@ -284,6 +284,11 @@ static const struct soc_amd_gpio romstage_gpio_table[] = { PAD_NC(GPIO_70), /* PCIE_RST0_L */ PAD_NFO(GPIO_26, PCIE_RST_L, HIGH), + /* Enable touchscreen, hold in reset */ + /* EN_PP3300_TCHSCR */ + PAD_GPO(GPIO_68, HIGH), + /* TCHSCR_RESET_L */ + PAD_GPO(GPIO_121, LOW), }; const struct soc_amd_gpio *baseboard_romstage_gpio_table(size_t *size) |