diff options
| author | Bill XIE <persmule@hardenedlinux.org> | 2023-10-27 18:58:15 +0800 |
|---|---|---|
| committer | Matt DeVillier <matt.devillier@amd.corp-partner.google.com> | 2023-10-29 14:21:02 +0000 |
| commit | c557847a9ecd95b3282622e37e566213963200e6 (patch) | |
| tree | 62d776a28d61f333be157bbf203c18f7d650a14b | |
| parent | a6cfb336f2085481975eab9789c7ac78feb8b4e1 (diff) | |
mb/lenovo/t430: Disable SuperSpeed capabilities for WWAN USB
Just as in commit 38569d061099: ("mb/lenovo/{x230, x230s}: Disable
SuperSpeed capabilities for WWAN USB")
Although on ThinkPads with Panther Point PCH the usb port inside wwan
socket is usually wired to XHCI, it has actually no SuperSpeed lines,
so maybe it is okay to disable SuperSpeed capabilities, and wire them
to EHCI #2 by making use of XUSB2PRM and USB3PRM.
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I61e61283a821686558f7f3fdfac7073bb3557e93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78680
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/lenovo/t430/devicetree.cb | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index 35c23b82c8..73fd5b20cc 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -28,9 +28,11 @@ chip northbridge/intel/sandybridge register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x17" - register "superspeed_capable_ports" = "0x0000000f" + + # Do not enable xHCI Port 4 since WWAN USB is EHCI-only + register "superspeed_capable_ports" = "0x7" + register "xhci_switchable_ports" = "0x7" register "xhci_overcurrent_mapping" = "0x04000201" - register "xhci_switchable_ports" = "0x0000000f" # device specific SPI configuration register "spi_uvscc" = "0x2005" |