diff options
| author | Sean Rhodes <sean@starlabs.systems> | 2023-08-16 09:04:00 +0100 |
|---|---|---|
| committer | Matt DeVillier <matt.devillier@amd.corp-partner.google.com> | 2023-08-17 16:45:31 +0000 |
| commit | c51e1682d575287a7b2844e94687cff4fdc4a2e7 (patch) | |
| tree | 42229b259963629c5f14465e62ec974a78c29eff | |
| parent | 676ef5b38ba44623ce007f120cae1ba3f4572e8f (diff) | |
mb/starlabs/starbook/rpl: Fix the Thunderbolt cmos option
For Thunderbolt to be disabled, `UsbTcPortEn` and `TcssXhciEn`
also need to be disabled.
Change-Id: Ie02c1e0ea7583bbd78e25c8184e2cdf2b6281741
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
3 files changed, 13 insertions, 0 deletions
diff --git a/src/mainboard/starlabs/starbook/variants/rpl/Makefile.inc b/src/mainboard/starlabs/starbook/variants/rpl/Makefile.inc index 2a505c35c7..9abc069b38 100644 --- a/src/mainboard/starlabs/starbook/variants/rpl/Makefile.inc +++ b/src/mainboard/starlabs/starbook/variants/rpl/Makefile.inc @@ -7,3 +7,4 @@ romstage-y += romstage.c ramstage-y += devtree.c ramstage-y += gpio.c ramstage-y += hda_verb.c +ramstage-y += ramstage.c diff --git a/src/mainboard/starlabs/starbook/variants/rpl/ramstage.c b/src/mainboard/starlabs/starbook/variants/rpl/ramstage.c new file mode 100644 index 0000000000..bd3d7edd43 --- /dev/null +++ b/src/mainboard/starlabs/starbook/variants/rpl/ramstage.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <option.h> +#include <soc/ramstage.h> + + +void mainboard_silicon_init_params(FSP_S_CONFIG *supd) +{ + if (get_uint_option("thunderbolt", 1) == 0) + supd->UsbTcPortEn = 0; +} diff --git a/src/mainboard/starlabs/starbook/variants/rpl/romstage.c b/src/mainboard/starlabs/starbook/variants/rpl/romstage.c index e51bd53be2..e7e1c6a3d2 100644 --- a/src/mainboard/starlabs/starbook/variants/rpl/romstage.c +++ b/src/mainboard/starlabs/starbook/variants/rpl/romstage.c @@ -40,6 +40,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) mupd->FspmConfig.VtdBaseAddress[3] = 0; mupd->FspmConfig.TcssDma0En = 0; mupd->FspmConfig.TcssItbtPcie0En = 0; + mupd->FspmConfig.TcssXhciEn = 0; } mupd->FspmConfig.DmiMaxLinkSpeed = 4; |