diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-03-05 16:40:25 -0700 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-03-08 18:25:11 +0000 |
| commit | c4e9c4e5547815d0146db130daafbde302997d48 (patch) | |
| tree | ba2545e5e25df7840af1409a4796a21e6ad80376 | |
| parent | 812b54ef1792d4995969c9519834c95330adde7e (diff) | |
mb/google/brya: Finish support for ChromeOS GPIOs
BUG=b:181887865
TEST=`crossystem` shows correct state of WP signal when toggled
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: If49ca1d70cc36ab74d70e858336679c0a9a3258e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
| -rw-r--r-- | src/mainboard/google/brya/chromeos.c | 4 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h | 4 |
2 files changed, 6 insertions, 2 deletions
diff --git a/src/mainboard/google/brya/chromeos.c b/src/mainboard/google/brya/chromeos.c index 5b098b52ff..add73464da 100644 --- a/src/mainboard/google/brya/chromeos.c +++ b/src/mainboard/google/brya/chromeos.c @@ -12,14 +12,14 @@ void fill_lb_gpios(struct lb_gpios *gpios) {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), "EC in RW"}, }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } int get_write_protect_state(void) { - /* No write protect */ - return 0; + return gpio_get(GPIO_PCH_WP); } void mainboard_chromeos_acpi_generate(void) diff --git a/src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h index 2024e488b9..96e88b56d1 100644 --- a/src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/brya/variants/baseboard/include/baseboard/gpio.h @@ -10,5 +10,9 @@ #define EC_SCI_GPI GPE0_ESPI /* EC wake is EC_PCH_INT which is routed to GPP_F17 pin */ #define GPE_EC_WAKE GPE0_DW2_17 +/* WP signal to PCH */ +#define GPIO_PCH_WP GPP_E15 +/* EC in RW or RO */ +#define GPIO_EC_IN_RW GPP_F18 #endif /* __BASEBOARD_GPIO_H__ */ |