diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2021-06-03 22:04:00 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2021-06-04 18:25:16 +0000 |
| commit | c11d4fb0b032504816ff69766b27b8889f067327 (patch) | |
| tree | 1754841746f1874439b79d548b02d616daac9f38 | |
| parent | 2e665eb8daa2963c52092e694a5316dc544a23f5 (diff) | |
mb/google/brya: Remove I2C4 usage in devicetree.cb
I2C4 is not used pn Brya hence make below changes:
1. Disable it in SerialIoI2cMode.
2. Remove I2C4 config in common_soc_config.
TEST=Make sure FSP is not programming I2C4.
Change-Id: I94c72b7fac9d8a001913b5faa2c0c8a3e8b701e9
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
| -rw-r--r-- | src/mainboard/google/brya/variants/baseboard/devicetree.cb | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb index 36635fb9aa..5b2ec14388 100644 --- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb @@ -68,7 +68,7 @@ chip soc/intel/alderlake [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoPci, [PchSerialIoIndexI2C3] = PchSerialIoPci, - [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, [PchSerialIoIndexI2C5] = PchSerialIoPci, }" @@ -118,9 +118,6 @@ chip soc/intel/alderlake .early_init = 1, .speed = I2C_SPEED_FAST, }, - .i2c[4] = { - .speed = I2C_SPEED_FAST, - }, .i2c[5] = { .speed = I2C_SPEED_FAST, }, |