diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-12-06 14:03:07 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-12-10 08:01:09 +0000 |
| commit | c0f4b1258dee579070be43c13f0f9fbc1313388b (patch) | |
| tree | 278b78358014316baeddf9e6301853a624f9067b | |
| parent | 64dd9d000e369761e2da9d7b53e60c3296bd1890 (diff) | |
soc/intel/meteorlake: Support PCIe hardware compliance test mode
The validation process verifies that hardware components comply with
the standard hardware specifications. For instance, PCI express
implementation must comply with the hardware PCIe specification
requirements: Electrical, Configuration, Link Protocol and Transaction
Protocol. To perform these tests the hardware must be configured in a
particular state: some feature related to power management need to be
turned off, hot plug should be enabled...
This patch sets the appropriate FSP Updateable Product Data flags to
get the hardware in the proper configuration:
- Enable PCIe hotplug on all ports
- Set clock sources to run free
- Set the FSP compliance test mode flag
This patch is backported from
commit 096ce1444ec7fa204f331a75c2ac9d00ea00bf12 (soc/intel/alderlake:
Support PCIe hardware compliance test mode)
Change-Id: Idd7a1adf0f53b014093ba70fee599dbb7887a0fc
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70416
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/meteorlake/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/meteorlake/fsp_params.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/meteorlake/romstage/fsp_params.c | 4 |
3 files changed, 8 insertions, 1 deletions
diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 79a51baea1..6b40b6698f 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -28,6 +28,7 @@ config CPU_SPECIFIC_OPTIONS select GENERIC_GPIO_LIB select HAVE_DEBUG_RAM_SETUP select HAVE_FSP_GOP + select HAVE_INTEL_COMPLIANCE_TEST_MODE select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE select INTEL_CAR_NEM diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index ad6d4bb092..53220ec96b 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -375,9 +375,11 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg, get_l1_substate_control(rp_cfg->PcieRpL1Substates); s_cfg->PcieRpLtrEnable[i] = !!(rp_cfg->flags & PCIE_RP_LTR); s_cfg->PcieRpAdvancedErrorReporting[i] = !!(rp_cfg->flags & PCIE_RP_AER); - s_cfg->PcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG); + s_cfg->PcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG) + || CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE); s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT); } + s_cfg->PcieComplianceTestMode = CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE); } static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg, diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index 7453eb0222..d104cb3bc1 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -31,6 +31,10 @@ static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask, static unsigned int clk_req_mapping = 0; for (i = 0; i < cfg_count; i++) { + if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE)) { + m_cfg->PcieClkSrcUsage[i] = FSP_CLK_FREE_RUNNING; + continue; + } if (!(en_mask & BIT(i))) continue; if (cfg[i].flags & PCIE_RP_CLK_SRC_UNUSED) |