diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-02-03 01:41:16 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-02-04 19:11:53 +0000 |
| commit | bee5c6084cd7555beefd933e44f6c2b67365f563 (patch) | |
| tree | 0a45bb9d2fb0fdabac20bf9b49d7396f58ba9621 | |
| parent | 8e1bb93fb88bc9cc20aab33a1fe09fb4c0c652a0 (diff) | |
soc/amd/phoenix/chipset.cb: add missing GPP bridges on device 1
Only the PCIe ports on the functions of device 2 were present in the
devicetree and had the amd_external_pcie_gpp_ops ops assigned. Add the
missing PCIe ports on the functions of device 1 and assign the
amd_external_pcie_gpp_ops ops to them.
This SoC uses a slightly different naming scheme for its PCIe GPP ports.
Previously the PCIe GPP bridge number from the PCI Device ID Assignments
table from the PPR was used. Those bridge numbers are one less than the
function numbers of the device. This is due to function 0 being a dummy
bridge to avoid having to shuffle around the function numbers when the
first bridge is unused, since the PCIe specification mandates the
function 0 to be implemented if any other function on the same device is
implemented. In order for the device aliases to be consistent with the
PCIe device and function numbers which is way more commonly used and
also what lspci shows and what goes into the DXIO descriptors, change
the naming scheme of the aliases.
This was checked with PPR #57019 Rev 1.65 and PPR #57396 Rev 1.54.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib5c62c1df585877d9b6986a462a3636d4f2eb4c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72736
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/amd/phoenix/chipset.cb | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/soc/amd/phoenix/chipset.cb b/src/soc/amd/phoenix/chipset.cb index 5c341c8783..47b393d030 100644 --- a/src/soc/amd/phoenix/chipset.cb +++ b/src/soc/amd/phoenix/chipset.cb @@ -9,7 +9,12 @@ chip soc/amd/phoenix device pci 00.0 alias gnb on ops phoenix_root_complex_operations end device pci 00.2 alias iommu off ops amd_iommu_ops end - device pci 01.0 on end # Dummy Host Bridge + device pci 01.0 on end # Dummy Host Bridge, do not disable + # The PCIe GPP aliases in this SoC match the device and function numbers + device pci 01.1 alias gpp_bridge_1_1 off ops amd_external_pcie_gpp_ops end + device pci 01.2 alias gpp_bridge_1_2 off ops amd_external_pcie_gpp_ops end + device pci 01.3 alias gpp_bridge_1_3 off ops amd_external_pcie_gpp_ops end + device pci 01.4 alias gpp_bridge_1_4 off ops amd_external_pcie_gpp_ops end device pci 02.0 on end # Dummy Host Bridge, do not disable device pci 02.1 alias gpp_bridge_0 off ops amd_external_pcie_gpp_ops end |