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authorHarsha B R <harsha.b.r@intel.com>2022-11-22 21:17:14 +0530
committerSubrata Banik <subratabanik@google.com>2022-12-27 10:42:07 +0000
commitbd91aa760945cf6229e4ce5e0acc5ed7cd60b398 (patch)
treee78e7d9a8f1ae043ee412a454eea03cb0ad8cb57
parentb052683d463a6c0afee4e233812e72f4f1e61ed2 (diff)
mb/intel/mtlrvp: Add bootblock and early gpio for MTL-RVP
This patch adds initial bootblock code. This also configures required GPIOs for early board initialization. 1. Add bootblock file for MTL-RVP 2. Add early gpio config for MTL-P variant in gpio.c BRANCH=none BUG=b:224325352 TEST=Able to build with the patch and boot the mtlrvp platform to ChromeOS with the subsequent patches in the train Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I9c0893e52036147c5f6bbfafc6d818e9d3460bed Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
-rw-r--r--src/mainboard/intel/mtlrvp/Makefile.inc2
-rw-r--r--src/mainboard/intel/mtlrvp/bootblock.c9
-rw-r--r--src/mainboard/intel/mtlrvp/variants/baseboard/include/baseboard/variants.h3
-rw-r--r--src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/Makefile.inc1
-rw-r--r--src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/gpio.c59
5 files changed, 74 insertions, 0 deletions
diff --git a/src/mainboard/intel/mtlrvp/Makefile.inc b/src/mainboard/intel/mtlrvp/Makefile.inc
index 0bd89131ba..e2fba1a78b 100644
--- a/src/mainboard/intel/mtlrvp/Makefile.inc
+++ b/src/mainboard/intel/mtlrvp/Makefile.inc
@@ -2,6 +2,8 @@
all-$(CONFIG_CHROMEOS) += chromeos.c
+bootblock-y += bootblock.c
+
ramstage-y += ec.c
ramstage-y += mainboard.c
diff --git a/src/mainboard/intel/mtlrvp/bootblock.c b/src/mainboard/intel/mtlrvp/bootblock.c
new file mode 100644
index 0000000000..2eea8ecf8f
--- /dev/null
+++ b/src/mainboard/intel/mtlrvp/bootblock.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <bootblock_common.h>
+
+void bootblock_mainboard_early_init(void)
+{
+ configure_early_gpio_pads();
+}
diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/mtlrvp/variants/baseboard/include/baseboard/variants.h
index 9ce216c8b0..da0e62823e 100644
--- a/src/mainboard/intel/mtlrvp/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/intel/mtlrvp/variants/baseboard/include/baseboard/variants.h
@@ -12,4 +12,7 @@ enum mtl_boardid {
MTLM_LP5_RVP = 0x06,
};
+/* Functions to configure GPIO as per variant schematics */
+void configure_early_gpio_pads(void);
+
#endif /*__BASEBOARD_VARIANTS_H__ */
diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/Makefile.inc b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/Makefile.inc
index eb2c9bc021..cc5cdc1ace 100644
--- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/Makefile.inc
+++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/Makefile.inc
@@ -1,3 +1,4 @@
## SPDX-License-Identifier: GPL-2.0-or-later
+bootblock-y += gpio.c
ramstage-y += gpio.c
diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/gpio.c b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/gpio.c
index 3e41a46a7d..87ff135152 100644
--- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/gpio.c
+++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/gpio.c
@@ -1,8 +1,67 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <console/console.h>
+#include <ec/intel/board_id.h>
+#include <soc/soc_info.h>
#include <vendorcode/google/chromeos/chromeos.h>
+/* Early pad configuration in bootblock */
+static const struct pad_config mtl_p_rvp_early_gpio_table[] = {
+ /* Audio */
+ PAD_NC(GPP_D14, NONE), /* M.2_BT_I2S2_PCMCLK/NONE */
+ PAD_NC(GPP_D15, NONE), /* M.2_BT_I2S2_PCMFRM/NONE */
+ PAD_CFG_GPO(GPP_S04, 1, DEEP), /* EN_SPKR_PA */
+ PAD_CFG_GPI_INT(GPP_S05, NONE, PLTRST, EDGE_BOTH),
+
+ /* SMBUS */
+ PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), /* GPP_C0_SMBCLK */
+ PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), /* GPP_C1_SMBDATA */
+
+ /* SSD */
+ PAD_CFG_GPO(GPP_B15, 0, DEEP), /* M.2_CPU_SSD3_PWREN */
+ PAD_CFG_GPO(GPP_D06, 0, DEEP), /* M.2_CPU_SSD4_PWREN */
+};
+
+static const struct pad_config early_uart_gpio_table[] = {
+ /* UART0 */
+ PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), /* UART0_RXD */
+ PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), /* UART0_TXD */
+};
+
+static const struct pad_config early_wwan_on_gpio_table[] = {
+ /* M.2 WWAN */
+ PAD_CFG_GPO(GPP_B17, 1, DEEP), /* WWAN_PWREN */
+ PAD_CFG_GPO(GPP_E07, 1, DEEP), /* M.2_WWAN_FCP_OFF_N */
+ PAD_CFG_GPO(GPP_A15, 0, DEEP), /* M.2_WWAN_RST_N */
+ PAD_CFG_GPO(GPP_C05, 0, DEEP), /* M.2_WWAN_PERST_GPIO_N */
+ PAD_CFG_GPI_SCI(GPP_F10, NONE, DEEP, LEVEL, INVERT), /* M.2_WWAN_WAKE_GPIO_N */
+};
+
+void configure_early_gpio_pads(void)
+{
+ uint8_t board_id = get_rvp_board_id();
+
+ if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE))
+ gpio_configure_pads(early_uart_gpio_table, ARRAY_SIZE(early_uart_gpio_table));
+
+ switch (board_id) {
+ case MTLP_DDR5_RVP:
+ case MTLP_LP5_T3_RVP:
+ case MTLP_LP5_T4_RVP:
+ gpio_configure_pads(mtl_p_rvp_early_gpio_table,
+ ARRAY_SIZE(mtl_p_rvp_early_gpio_table));
+ gpio_configure_pads(early_wwan_on_gpio_table,
+ ARRAY_SIZE(early_wwan_on_gpio_table));
+ break;
+ default:
+ printk(BIOS_WARNING, "Invalid board_id 0x%x."
+ "Skipping early gpio configuration\n", board_id);
+ break;
+ }
+}
+
static const struct cros_gpio cros_gpios[] = {
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
};