diff options
| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2023-10-02 07:18:18 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-10-09 14:08:05 +0000 |
| commit | bd7a7fd4b2e0244e1d8f08b998825429f9937323 (patch) | |
| tree | f74cf6807253cc4d90a711e649fd9bd042cc4d8e | |
| parent | 91c38146a4493833a5a7c7a11d251a77b028858d (diff) | |
sb/intel/bd82x6x: Use helper for PCIe hotplug
Introduce pci_is_hotplugable is helper to find hotpluggable
PCIe devices.
Test: PCI express slot is still marked as the only hotpluggable
PCIe root port.
Change-Id: I25aae540ff2ffa3ec5b93ed9caa838b4e50048d2
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78227
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pcie.c | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index 6f082e8107..206894d8a4 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -32,6 +32,13 @@ static const char *pch_pcie_acpi_name(const struct device *dev) return NULL; } +static bool pci_is_hotplugable(struct device *dev) +{ + struct southbridge_intel_bd82x6x_config *config = dev->chip_info; + + return config && config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]; +} + static void pch_pcie_pm_early(struct device *dev) { u16 link_width_p0, link_width_p4; @@ -179,7 +186,6 @@ static void pch_pcie_pm_late(struct device *dev) static void pci_init(struct device *dev) { u16 reg16; - struct southbridge_intel_bd82x6x_config *config = dev->chip_info; printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n"); @@ -202,7 +208,7 @@ static void pci_init(struct device *dev) pci_write_config16(dev, 0x1e, reg16); /* Enable expresscard hotplug events. */ - if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) { + if (pci_is_hotplugable(dev)) { pci_or_config32(dev, 0xd8, 1 << 30); pci_write_config16(dev, 0x42, 0x142); } @@ -216,9 +222,7 @@ static void pch_pcie_enable(struct device *dev) static void pch_pciexp_scan_bridge(struct device *dev) { - struct southbridge_intel_bd82x6x_config *config = dev->chip_info; - - if (CONFIG(PCIEXP_HOTPLUG) && config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) { + if (CONFIG(PCIEXP_HOTPLUG) && pci_is_hotplugable(dev)) { pciexp_hotplug_scan_bridge(dev); } else { /* Normal PCIe Scan */ |