diff options
| author | Van Chen <van_chen@compal.corp-partner.google.com> | 2023-11-20 12:05:20 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-11-22 17:53:25 +0000 |
| commit | bbb6d5d4777fe75ee94f35a1c290c361086ed035 (patch) | |
| tree | 8265d58feaf5613e912b4993a053ebd3987cee4e | |
| parent | 4b5ab3e7341dfc42f5224bd93b895c8ccf01e1e6 (diff) | |
mb/google/nissa/var/craaskov: Add 6W and 15W DPTF parameters
The DPTF parameters were defined by the thermal team.
Based on thermal table in 290705146#comment17.
BUG=b:290705146
BRUNCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I02b4187000eec9990bf10a57875b23007f7bdd12
Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79183
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/google/brya/variants/craaskov/overridetree.cb | 97 |
1 files changed, 94 insertions, 3 deletions
diff --git a/src/mainboard/google/brya/variants/craaskov/overridetree.cb b/src/mainboard/google/brya/variants/craaskov/overridetree.cb index 8c29567069..c9299de0cc 100644 --- a/src/mainboard/google/brya/variants/craaskov/overridetree.cb +++ b/src/mainboard/google/brya/variants/craaskov/overridetree.cb @@ -1,3 +1,10 @@ +fw_config + field THERMAL_SOLUTION 0 0 + option THERMAL_SOLUTION_6W 0 + option THERMAL_SOLUTION_15W 1 + end +end + chip soc/intel/alderlake register "sagv" = "SaGv_Enabled" @@ -99,6 +106,22 @@ chip soc/intel/alderlake register "options.tsr[1].desc" = ""charger"" register "options.tsr[2].desc" = ""ambient"" + ## Active Policy + register "policies.active" = "{ + [0] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(0, 0), + TEMP_PCT(35, 27), + TEMP_PCT(38, 31), + TEMP_PCT(39, 35), + TEMP_PCT(42, 41), + TEMP_PCT(60, 47), + TEMP_PCT(70, 100), + } + } + }" + ## Passive Policy register "policies.passive" = "{ [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), @@ -117,8 +140,8 @@ chip soc/intel/alderlake register "controls.power_limits" = "{ .pl1 = { - .min_power = 5500, - .max_power = 6000, + .min_power = 6000, + .max_power = 20000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 28 * MSECS_PER_SEC, .granularity = 500 @@ -139,7 +162,75 @@ chip soc/intel/alderlake [2] = { 16, 1000 }, [3] = { 8, 500 } }" - device generic 0 on end + device generic 0 on + probe THERMAL_SOLUTION THERMAL_SOLUTION_6W + end + end + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DDR"" + register "options.tsr[1].desc" = ""charger"" + register "options.tsr[2].desc" = ""ambient"" + + ## Active Policy + register "policies.active" = "{ + [0] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(0, 0), + TEMP_PCT(35, 27), + TEMP_PCT(38, 31), + TEMP_PCT(39, 35), + TEMP_PCT(42, 41), + TEMP_PCT(60, 47), + TEMP_PCT(70, 100), + } + } + }" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 70, 5000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 70, 5000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 15000, + .max_power = 20000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 28 * MSECS_PER_SEC, + .granularity = 500 + }, + .pl2 = { + .min_power = 35000, + .max_power = 35000, + .time_window_min = 32 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 500 + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + device generic 1 on + probe THERMAL_SOLUTION THERMAL_SOLUTION_15W + end end end device ref i2c1 on |