Correct "MTTR" to "MTRR"

The term MTRR has been misspelled in a few places.

Change-Id: I3e3c11f80de331fa45ae89779f2b8a74a0097c74
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

7 files changed, 16 insertions, 16 deletions

diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index 532dd5d698..c8b913cb83 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -427,7 +427,7 @@ static void prep_var_mtrr(struct var_mtrr_state *var_state,
 	if (var_state->mtrr_index >= bios_mtrrs)
 		printk(BIOS_WARNING, "Taking a reserved OS MTRR.\n");
 	if (var_state->mtrr_index >= total_mtrrs) {
-		printk(BIOS_ERR, "ERROR: Not enough MTRRs available! MTRR index is %d with %d MTTRs in total.\n",
+		printk(BIOS_ERR, "ERROR: Not enough MTRRs available! MTRR index is %d with %d MTRRs in total.\n",
 		       var_state->mtrr_index, total_mtrrs);
 		return;
 	}
diff --git a/src/drivers/intel/fsp1_1/stack.c b/src/drivers/intel/fsp1_1/stack.c
index 639cf38211..e4b30dd872 100644
--- a/src/drivers/intel/fsp1_1/stack.c
+++ b/src/drivers/intel/fsp1_1/stack.c
@@ -36,7 +36,7 @@ void *setup_stack_and_mtrrs(void)
 	uint32_t num_mtrrs;
 	uint32_t *slot;
 
-	/* Display the MTTRs */
+	/* Display the MTRRs */
 	soc_display_mtrrs();
 
 	/* Top of stack needs to be aligned to a 8-byte boundary. */
diff --git a/src/soc/intel/broadwell/romstage/stack.c b/src/soc/intel/broadwell/romstage/stack.c
index f17cd82d05..a6a4b4bfc9 100644
--- a/src/soc/intel/broadwell/romstage/stack.c
+++ b/src/soc/intel/broadwell/romstage/stack.c
@@ -47,18 +47,18 @@ void *setup_stack_and_mttrs(void)
 	 * of physical address bits. */
 	mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1;
 
-	/* The order for each MTTR is value then base with upper 32-bits of
+	/* The order for each MTRR is value then base with upper 32-bits of
 	 * each value coming before the lower 32-bits. The reasoning for
 	 * this ordering is to create a stack layout like the following:
 	 *   +0: Number of MTRRs
-	 *   +4: MTTR base 0 31:0
-	 *   +8: MTTR base 0 63:32
-	 *  +12: MTTR mask 0 31:0
-	 *  +16: MTTR mask 0 63:32
-	 *  +20: MTTR base 1 31:0
-	 *  +24: MTTR base 1 63:32
-	 *  +28: MTTR mask 1 31:0
-	 *  +32: MTTR mask 1 63:32
+	 *   +4: MTRR base 0 31:0
+	 *   +8: MTRR base 0 63:32
+	 *  +12: MTRR mask 0 31:0
+	 *  +16: MTRR mask 0 63:32
+	 *  +20: MTRR base 1 31:0
+	 *  +24: MTRR base 1 63:32
+	 *  +28: MTRR mask 1 31:0
+	 *  +32: MTRR mask 1 63:32
 	 */
 
 	/* Cache the ROM as WP just below 4GiB. */
@@ -97,7 +97,7 @@ void *setup_stack_and_mttrs(void)
 	slot = stack_push(slot, top_of_ram | MTRR_TYPE_WRBACK);
 	num_mtrrs++;
 
-	/* Save the number of MTTRs to setup. Return the stack location
+	/* Save the number of MTRRs to setup. Return the stack location
 	 * pointing to the number of MTRRs. */
 	slot = stack_push(slot, num_mtrrs);
 
diff --git a/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc
index fc7d0e461f..f444852e54 100644
--- a/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc
+++ b/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc
@@ -1348,7 +1348,7 @@ SetupStack:
     mov     $TOP_MEM2, %ecx               # MSR:C001_001D
     _WRMSR
 
-    # setup MTTRs for stacks
+    # setup MTRRs for stacks
     #   A speculative read can be generated by a speculative fetch mis-aligned in a code zone
     #    or due to a data zone being interpreted as code. When a speculative read occurs outside a
     #    controlled region (intentionally used by software), it could cause an unwanted cache eviction.
diff --git a/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc
index 45ed2948e7..0fbcf77eea 100644
--- a/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc
+++ b/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc
@@ -1084,7 +1084,7 @@ SetupStack:
     mov     $TOP_MEM2, %ecx               # MSR:C001_001D
     _WRMSR
 
-    # setup MTTRs for stacks
+    # setup MTRRs for stacks
     #   A speculative read can be generated by a speculative fetch mis-aligned in a code zone
     #    or due to a data zone being interpreted as code. When a speculative read occurs outside a
     #    controlled region (intentionally used by software), it could cause an unwanted cache eviction.
diff --git a/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc
index c744e47a03..2399bec91b 100644
--- a/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc
+++ b/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc
@@ -1063,7 +1063,7 @@ SetupStack:
     mov     $TOP_MEM2, %ecx               # MSR:C001_001D
     _WRMSR
 
-    # setup MTTRs for stacks
+    # setup MTRRs for stacks
     #   A speculative read can be generated by a speculative fetch mis-aligned in a code zone
     #    or due to a data zone being interpreted as code. When a speculative read occurs outside a
     #    controlled region (intentionally used by software), it could cause an unwanted cache eviction.
diff --git a/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc
index 5a4f7b9290..7e12db1d06 100644
--- a/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc
+++ b/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc
@@ -1063,7 +1063,7 @@ SetupStack:
     mov     $TOP_MEM2, %ecx               # MSR:C001_001D
     _WRMSR
 
-    # setup MTTRs for stacks
+    # setup MTRRs for stacks
     #   A speculative read can be generated by a speculative fetch mis-aligned in a code zone
     #    or due to a data zone being interpreted as code. When a speculative read occurs outside a
     #    controlled region (intentionally used by software), it could cause an unwanted cache eviction.