diff options
| author | Felix Singer <felixsinger@posteo.net> | 2024-06-23 04:37:30 +0200 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2024-06-24 14:23:34 +0000 |
| commit | ba7569c10b2aa37083242d8969edc5241cabaffa (patch) | |
| tree | f963cffe79b0340dbc6a031608d4d293e1174ce9 | |
| parent | 00e137694367a0db3606b3c6a887f49356e2a440 (diff) | |
skl mainboards/dt: Drop SataPortsDevSlp[x] setting if disabled
The attributes are initialized with 0 and thus setting them to 0 makes
them superfluous. Remove them.
Change-Id: I572a9092633c61907794ecbbbe431066d889c5fb
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
| -rw-r--r-- | src/mainboard/libretrend/lt1000/devicetree.cb | 5 | ||||
| -rw-r--r-- | src/mainboard/protectli/vault_kbl/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/purism/librem_skl/devicetree.cb | 2 |
3 files changed, 0 insertions, 9 deletions
diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index 2cb674f486..dd2fc6084c 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -38,11 +38,6 @@ chip soc/intel/skylake [1] = 1, [2] = 1, }" - register "SataPortsDevSlp" = "{ - [0] = 0, - [1] = 0, - [2] = 0, - }" register "SataSpeedLimit" = "2" register "DspEnable" = "1" register "IoBufferOwnership" = "0" diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index b824fb4b1b..f57f97832c 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -109,8 +109,6 @@ chip soc/intel/skylake # Enable SATA ports 1,2 register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" - register "SataPortsDevSlp[0]" = "0" - register "SataPortsDevSlp[1]" = "0" # Enable Root ports. 1-6 for LAN and Root Port 9 register "PcieRpEnable[0]" = "1" diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 0083e641a5..03d48faaa1 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -43,8 +43,6 @@ chip soc/intel/skylake # FSP Configuration register "SataPortsEnable[0]" = "1" register "SataPortsEnable[2]" = "1" - register "SataPortsDevSlp[0]" = "0" - register "SataPortsDevSlp[2]" = "0" register "DspEnable" = "0" register "IoBufferOwnership" = "0" register "SkipExtGfxScan" = "1" |