mb/google/volteer/var/volet: add volet memory configuration.

volet use same memory configuration from Voxel, copy voxel setting to
volet.

BUG=b:186334008
TEST=FW_NAME=volet emerge-volteer coreboot chromeos-bootimage

Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I7e65b18f2ddae3d1ce02d9006153269697188f61
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55096
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

5 files changed, 81 insertions, 13 deletions

diff --git a/src/mainboard/google/volteer/variants/volet/Makefile.inc b/src/mainboard/google/volteer/variants/volet/Makefile.inc
new file mode 100644
index 0000000000..9064208bff
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/volet/Makefile.inc
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+romstage-y += memory.c
diff --git a/src/mainboard/google/volteer/variants/volet/memory.c b/src/mainboard/google/volteer/variants/volet/memory.c
new file mode 100644
index 0000000000..fe2b2b1999
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/volet/memory.c
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+
+static const struct mb_cfg board_memcfg = {
+	.type = MEM_TYPE_LP4X,
+
+	/* DQ byte map */
+	.lp4x_dq_map = {
+		.ddr0 = {
+			.dq0 = { 3,  0,  1,  2,  6,  7,  5,  4, }, /* DDR0_DQ0[7:0] */
+			.dq1 = { 12, 15, 14,  13, 8,  9, 10, 11 }, /* DDR0_DQ1[7:0] */
+		},
+		.ddr1 = {
+			.dq0 = { 12,  15,  13,  14,  10,  8,  11,  9, }, /* DDR1_DQ0[7:0] */
+			.dq1 = { 5, 6, 7, 4,  0, 3, 1, 2  }, /* DDR1_DQ1[7:0] */
+		},
+		.ddr2 = {
+			.dq0 = { 2, 3, 0, 1,  7, 6, 5, 4, }, /* DDR2_DQ0[7:0] */
+			.dq1 = { 12,  14,  15,  13,  10,  9,  8,  11  }, /* DDR2_DQ1[7:0] */
+		},
+		.ddr3 = {
+			.dq0 = { 15, 12, 13, 14, 8, 9, 10,  11, }, /* DDR3_DQ0[7:0] */
+			.dq1 = { 7,  6,  4,  5,  2,  0,  3,  1  }, /* DDR3_DQ1[7:0] */
+		},
+		.ddr4 = {
+			.dq0 = { 6,  5,  4,  7,  0,  3,  2,  1, }, /* DDR4_DQ0[7:0] */
+			.dq1 = { 15, 14,  13, 12, 11,  8, 9, 10 }, /* DDR4_DQ1[7:0] */
+		},
+		.ddr5 = {
+			.dq0 = { 11,  9,  10,  8,  12,  14,  13,  15, }, /* DDR5_DQ0[7:0] */
+			.dq1 = { 1, 0, 2, 3, 6, 7,  5,  4 }, /* DDR5_DQ1[7:0] */
+		},
+		.ddr6 = {
+			.dq0 = { 2, 3, 0, 1, 5,  4, 6, 7, }, /* DDR6_DQ0[7:0] */
+			.dq1 = { 13,  14,  15,  12,  11,  10,  8,  9  }, /* DDR6_DQ1[7:0] */
+		},
+		.ddr7 = {
+			.dq0 = { 14, 13, 15,  12, 9, 8, 10, 11, }, /* DDR7_DQ0[7:0] */
+			.dq1 = { 4,  5,  1,  2,  6,  0,  3,  7  }, /* DDR7_DQ1[7:0] */
+		},
+	},
+
+	/* DQS CPU<>DRAM map */
+	.lp4x_dqs_map = {
+		.ddr0 = { .dqs0 = 0, .dqs1 = 1 },  /* DDR0_DQS[1:0] */
+		.ddr1 = { .dqs0 = 1, .dqs1 = 0 },  /* DDR1_DQS[1:0] */
+		.ddr2 = { .dqs0 = 0, .dqs1 = 1 },  /* DDR2_DQS[1:0] */
+		.ddr3 = { .dqs0 = 1, .dqs1 = 0 },  /* DDR3_DQS[1:0] */
+		.ddr4 = { .dqs0 = 0, .dqs1 = 1 },  /* DDR4_DQS[1:0] */
+		.ddr5 = { .dqs0 = 1, .dqs1 = 0 },  /* DDR5_DQS[1:0] */
+		.ddr6 = { .dqs0 = 0, .dqs1 = 1 },  /* DDR6_DQS[1:0] */
+		.ddr7 = { .dqs0 = 1, .dqs1 = 0 },  /* DDR7_DQS[1:0] */
+	},
+
+	.ect = true, /* Enable Early Command Training */
+};
+
+const struct mb_cfg *variant_memory_params(void)
+{
+	return &board_memcfg;
+}
diff --git a/src/mainboard/google/volteer/variants/volet/memory/Makefile.inc b/src/mainboard/google/volteer/variants/volet/memory/Makefile.inc
index b0ca2223a8..f40fba6751 100644
--- a/src/mainboard/google/volteer/variants/volet/memory/Makefile.inc
+++ b/src/mainboard/google/volteer/variants/volet/memory/Makefile.inc
@@ -1,5 +1,7 @@
 ## SPDX-License-Identifier: GPL-2.0-or-later
 ## This is an auto-generated file. Do not edit!!
-## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate.
 
-SPD_SOURCES = placeholder.spd.hex
+SPD_SOURCES =
+SPD_SOURCES += lp4x-spd-1.hex      # ID = 0(0b0000)  Parts = MT53E512M32D2NP-046 WT:E, H9HCNNNBKMMLXR-NEE, K4U6E3S4AA-MGCR
+SPD_SOURCES += lp4x-spd-4.hex      # ID = 1(0b0001)  Parts = MT53E1G32D2NP-046 WT:A
+SPD_SOURCES += lp4x-spd-3.hex      # ID = 2(0b0010)  Parts = H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR
diff --git a/src/mainboard/google/volteer/variants/volet/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/volet/memory/dram_id.generated.txt
index fa247902ee..8d472df850 100644
--- a/src/mainboard/google/volteer/variants/volet/memory/dram_id.generated.txt
+++ b/src/mainboard/google/volteer/variants/volet/memory/dram_id.generated.txt
@@ -1 +1,7 @@
 DRAM Part Name                 ID to assign
+MT53E512M32D2NP-046 WT:E       0 (0000)
+H9HCNNNBKMMLXR-NEE             0 (0000)
+K4U6E3S4AA-MGCR                0 (0000)
+MT53E1G32D2NP-046 WT:A         1 (0001)
+H9HCNNNCPMMLXR-NEE             2 (0010)
+K4UBE3D4AA-MGCR                2 (0010)
diff --git a/src/mainboard/google/volteer/variants/volet/memory/mem_parts_used.txt b/src/mainboard/google/volteer/variants/volet/memory/mem_parts_used.txt
index e4258b530d..5ddd52ebba 100644
--- a/src/mainboard/google/volteer/variants/volet/memory/mem_parts_used.txt
+++ b/src/mainboard/google/volteer/variants/volet/memory/mem_parts_used.txt
@@ -1,11 +1,6 @@
-# This is a CSV file containing a list of memory parts used by this variant.
-# One part per line with an optional fixed ID in column 2.
-# Only include a fixed ID if it is required for legacy reasons!
-# Generated IDs are dependent on the order of parts in this file,
-# so new parts must always be added at the end of the file!
-#
-# Generate an updated Makefile.inc and dram_id.generated.txt by running the
-# gen_part_id tool from util/spd_tools/{ddr4,lp4x}.
-# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions.
-
-# Part Name
+MT53E512M32D2NP-046 WT:E
+H9HCNNNBKMMLXR-NEE
+K4U6E3S4AA-MGCR
+MT53E1G32D2NP-046 WT:A
+H9HCNNNCPMMLXR-NEE
+K4UBE3D4AA-MGCR