summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorElyes HAOUAS <ehaouas@noos.fr>2021-12-31 08:10:55 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-01-01 14:58:44 +0000
commitb7ec42d2ff28527690d8e9762cf13cb941bfd491 (patch)
treef28c57296f3f2e8ddc4eb4016e6f8ebd91ed20fe
parent8292f4160a80a391892a42c7305e5992d278d254 (diff)
src: Use 'stdint.h' when appropriate
Change-Id: I1df255d55b8f43a711d836c2565c367bd988098a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
-rw-r--r--src/mainboard/asrock/b85m_pro4/romstage.c1
-rw-r--r--src/mainboard/asrock/h81m-hds/romstage.c1
-rw-r--r--src/mainboard/google/beltino/romstage.c1
-rw-r--r--src/mainboard/hp/folio_9480m/romstage.c1
-rw-r--r--src/mainboard/intel/baskingridge/romstage.c1
-rw-r--r--src/mainboard/msi/h81m-p33/romstage.c1
-rw-r--r--src/mainboard/supermicro/x10slm-f/romstage.c1
-rw-r--r--src/northbridge/intel/gm45/early_init.c1
-rw-r--r--src/soc/intel/baytrail/include/soc/modphy_table.h2
-rw-r--r--src/soc/intel/baytrail/modphy_table.c1
-rw-r--r--src/southbridge/intel/i82801gx/early_init.c1
11 files changed, 2 insertions, 10 deletions
diff --git a/src/mainboard/asrock/b85m_pro4/romstage.c b/src/mainboard/asrock/b85m_pro4/romstage.c
index 75efb9e69c..25b157d8a3 100644
--- a/src/mainboard/asrock/b85m_pro4/romstage.c
+++ b/src/mainboard/asrock/b85m_pro4/romstage.c
@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <stdint.h>
#include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/raminit.h>
#include <southbridge/intel/lynxpoint/pch.h>
diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c
index cc9a04fad6..3573d690be 100644
--- a/src/mainboard/asrock/h81m-hds/romstage.c
+++ b/src/mainboard/asrock/h81m-hds/romstage.c
@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <stdint.h>
#include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/raminit.h>
#include <southbridge/intel/lynxpoint/pch.h>
diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c
index a818d87f1c..ecf54905e6 100644
--- a/src/mainboard/google/beltino/romstage.c
+++ b/src/mainboard/google/beltino/romstage.c
@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <stdint.h>
#include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/raminit.h>
#include <southbridge/intel/lynxpoint/pch.h>
diff --git a/src/mainboard/hp/folio_9480m/romstage.c b/src/mainboard/hp/folio_9480m/romstage.c
index f1df3ef1c0..fa7cba114d 100644
--- a/src/mainboard/hp/folio_9480m/romstage.c
+++ b/src/mainboard/hp/folio_9480m/romstage.c
@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <stdint.h>
#include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/raminit.h>
#include <southbridge/intel/lynxpoint/pch.h>
diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c
index 07a0083ae3..936703bce7 100644
--- a/src/mainboard/intel/baskingridge/romstage.c
+++ b/src/mainboard/intel/baskingridge/romstage.c
@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <stdint.h>
#include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/raminit.h>
#include <southbridge/intel/lynxpoint/pch.h>
diff --git a/src/mainboard/msi/h81m-p33/romstage.c b/src/mainboard/msi/h81m-p33/romstage.c
index 5a8f479431..f4db2644be 100644
--- a/src/mainboard/msi/h81m-p33/romstage.c
+++ b/src/mainboard/msi/h81m-p33/romstage.c
@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <stdint.h>
#include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/raminit.h>
#include <southbridge/intel/lynxpoint/pch.h>
diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c
index f7711c05ca..01dab69989 100644
--- a/src/mainboard/supermicro/x10slm-f/romstage.c
+++ b/src/mainboard/supermicro/x10slm-f/romstage.c
@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <stdint.h>
#include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/raminit.h>
#include <southbridge/intel/lynxpoint/pch.h>
diff --git a/src/northbridge/intel/gm45/early_init.c b/src/northbridge/intel/gm45/early_init.c
index 6e3ea2c7a3..e9110643f4 100644
--- a/src/northbridge/intel/gm45/early_init.c
+++ b/src/northbridge/intel/gm45/early_init.c
@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <stdint.h>
#include <device/pci_ops.h>
#include <southbridge/intel/i82801ix/i82801ix.h>
#include "gm45.h"
diff --git a/src/soc/intel/baytrail/include/soc/modphy_table.h b/src/soc/intel/baytrail/include/soc/modphy_table.h
index 9a483c4a6a..0561841a0b 100644
--- a/src/soc/intel/baytrail/include/soc/modphy_table.h
+++ b/src/soc/intel/baytrail/include/soc/modphy_table.h
@@ -3,6 +3,8 @@
#ifndef _BAYTRAIL_MODPHY_TABLE_H_
#define _BAYTRAIL_MODPHY_TABLE_H_
+#include <stdint.h>
+
struct modphy_entry {
u8 port;
u32 reg;
diff --git a/src/soc/intel/baytrail/modphy_table.c b/src/soc/intel/baytrail/modphy_table.c
index f028c8f3de..ebda7001e0 100644
--- a/src/soc/intel/baytrail/modphy_table.c
+++ b/src/soc/intel/baytrail/modphy_table.c
@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <stdint.h>
#include <soc/modphy_table.h>
struct modphy_entry reva0_modphy_table[] = { /* SOC stepping A0/A1 */
diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c
index c8a6117de5..4647bf1c6a 100644
--- a/src/southbridge/intel/i82801gx/early_init.c
+++ b/src/southbridge/intel/i82801gx/early_init.c
@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <stdint.h>
#include <console/console.h>
#include <device/pci_ops.h>
#include <device/smbus_host.h>