diff options
| author | Edward O'Callaghan <quasisec@google.com> | 2020-08-28 19:28:01 +1000 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2020-08-29 01:59:02 +0000 |
| commit | b656e9b71e2ce494568ad1389b04b7dbb085d7ee (patch) | |
| tree | ebfbe1795a768dbad962275e4ced24f17c8aaac6 | |
| parent | 07de90837363f2e4e58d08fe15ef41381f71815f (diff) | |
PCI IDs: Add PCI ID for CML DPTF/DTT PCI device
This PCI ID is required in order for the CML devices to perform
SSDT generation for DPTF.
CML Processor, EDS, Vol 1,
Table 9-5, Section 9.2.
BUG=b:158986928
BRANCH=puff
TEST=builds
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Change-Id: I94aea6b9e0f60656827daada7b2cc2741604b8b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Andrew McRae <amcrae@google.com>
| -rw-r--r-- | src/include/device/pci_ids.h | 1 | ||||
| -rw-r--r-- | src/soc/intel/common/block/dtt/dtt.c | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 04f9d2d1a7..f055e52914 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3968,6 +3968,7 @@ #define PCI_DEVICE_ID_INTEL_JSL_IPU 0x4e19 /* Intel Dynamic Tuning Technology Device */ +#define PCI_DEVICE_ID_INTEL_CML_DTT 0x1903 #define PCI_DEVICE_ID_INTEL_TGL_DTT 0x9A03 #define PCI_DEVICE_ID_INTEL_JSL_DTT 0x4E03 diff --git a/src/soc/intel/common/block/dtt/dtt.c b/src/soc/intel/common/block/dtt/dtt.c index f3969939c9..d92eb15c85 100644 --- a/src/soc/intel/common/block/dtt/dtt.c +++ b/src/soc/intel/common/block/dtt/dtt.c @@ -5,6 +5,7 @@ #include <device/pci_ids.h> static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_CML_DTT, PCI_DEVICE_ID_INTEL_TGL_DTT, PCI_DEVICE_ID_INTEL_JSL_DTT, }; |