diff options
| author | Joey Peng <joey.peng@lcfc.corp-partner.google.com> | 2023-03-14 14:20:55 +0800 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2023-03-16 15:00:50 +0000 |
| commit | b5fd92a14e9346fcd71830ddd2315bf610e3f935 (patch) | |
| tree | 4bcdf2f34a0fe558d94ed8dd46793eab417ae476 | |
| parent | 3e7008df950ddae0c280e1459d0d5e020eca9028 (diff) | |
mb/google/brya/var/taniks: Remove unused temp sensor setting
Rwmove temp sensor 3 for taniks since we do not use it.
BUG=b:265075696
TEST=emerge-brya coreboot, flash to DUT and will not see error messages
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Ib2c0cc8f1b2e65616c71d66632144ac89ca09fa1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
| -rw-r--r-- | src/mainboard/google/brya/variants/taniks/overridetree.cb | 13 |
1 files changed, 0 insertions, 13 deletions
diff --git a/src/mainboard/google/brya/variants/taniks/overridetree.cb b/src/mainboard/google/brya/variants/taniks/overridetree.cb index 63c74efdd0..acacec34fe 100644 --- a/src/mainboard/google/brya/variants/taniks/overridetree.cb +++ b/src/mainboard/google/brya/variants/taniks/overridetree.cb @@ -120,7 +120,6 @@ chip soc/intel/alderlake register "options.tsr[0].desc" = ""DRAM_SOC"" register "options.tsr[1].desc" = ""Ambient"" register "options.tsr[2].desc" = ""Charger"" - register "options.tsr[3].desc" = ""WWAN"" # TODO: below values are initial reference values only ## Active Policy @@ -155,16 +154,6 @@ chip soc/intel/alderlake TEMP_PCT(42, 40), } }, - [3] = { - .target = DPTF_TEMP_SENSOR_3, - .thresholds = { - TEMP_PCT(60, 69), - TEMP_PCT(56, 50), - TEMP_PCT(52, 50), - TEMP_PCT(46, 40), - TEMP_PCT(42, 40), - } - } }" ## Passive Policy @@ -173,7 +162,6 @@ chip soc/intel/alderlake [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 90, 6000), [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 90, 6000), [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 90, 6000), - [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 90, 6000), }" ## Critical Policy @@ -182,7 +170,6 @@ chip soc/intel/alderlake [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 100, SHUTDOWN), [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 100, SHUTDOWN), [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 100, SHUTDOWN), - [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 100, SHUTDOWN), }" register "controls.power_limits" = "{ |