diff options
| author | David Hendricks <dhendrix@chromium.org> | 2014-09-29 13:48:40 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@google.com> | 2015-04-04 04:03:18 +0200 |
| commit | b4ff291cf6999651cd29b3df671049feffeb5e48 (patch) | |
| tree | 84a7aa6ce4241645757982996a3b4b99ad8c0458 | |
| parent | f4305468d7c49698548babb7366a3b3d813771d2 (diff) | |
rk3288: Pass SPI bus speed in as parameter to init function
This re-factors rockchip_spi to remove speed_hz which will instead be
passed in via rockchip_spi_init(), thus making it easier to support
other boards which may have different slave devices attached.
BUG=none
BRANCH=none
TEST=built and booted on Pinky
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I7baf0fa0a2660e3c975847fdec3eb92bcd0d6c10
Original-Reviewed-on: https://chromium-review.googlesource.com/220411
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit de33d2ed6352fc4c8e81dc53451f164a8792daf2)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ie6473e47d50b7e633688185e8d8036980b833f1c
Reviewed-on: http://review.coreboot.org/9245
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
| -rw-r--r-- | src/mainboard/google/veyron_pinky/bootblock.c | 4 | ||||
| -rw-r--r-- | src/soc/rockchip/rk3288/spi.c | 8 | ||||
| -rw-r--r-- | src/soc/rockchip/rk3288/spi.h | 2 |
3 files changed, 5 insertions, 9 deletions
diff --git a/src/mainboard/google/veyron_pinky/bootblock.c b/src/mainboard/google/veyron_pinky/bootblock.c index 5e22d6e7d6..d4f82decff 100644 --- a/src/mainboard/google/veyron_pinky/bootblock.c +++ b/src/mainboard/google/veyron_pinky/bootblock.c @@ -32,11 +32,11 @@ void bootblock_mainboard_init(void) /* spi2 for firmware ROM */ writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk); writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx); - rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS); + rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11000000); /* spi0 for chrome ec */ writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0); - rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS); + rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 9000000); setup_chromeos_gpios(); } diff --git a/src/soc/rockchip/rk3288/spi.c b/src/soc/rockchip/rk3288/spi.c index 844d692aa4..3fb7291085 100644 --- a/src/soc/rockchip/rk3288/spi.c +++ b/src/soc/rockchip/rk3288/spi.c @@ -33,7 +33,6 @@ struct rockchip_spi_slave { struct spi_slave slave; struct rockchip_spi *regs; - unsigned int speed_hz; unsigned int fifo_size; }; @@ -47,13 +46,11 @@ static struct rockchip_spi_slave rockchip_spi_slaves[3] = { .rw = SPI_READ_FLAG | SPI_WRITE_FLAG, }, .regs = (void *)SPI0_BASE, - .speed_hz = 9000000, .fifo_size = 32, }, { .slave = {.bus = 1, .rw = SPI_READ_FLAG,}, .regs = (void *)SPI1_BASE, - .speed_hz = 11000000, .fifo_size = 32, }, { @@ -62,7 +59,6 @@ static struct rockchip_spi_slave rockchip_spi_slaves[3] = { .rw = SPI_READ_FLAG | SPI_WRITE_FLAG, }, .regs = (void *)SPI2_BASE, - .speed_hz = 11000000, .fifo_size = 32, }, @@ -110,7 +106,7 @@ static void rockchip_spi_set_clk(struct rockchip_spi *regs, unsigned int hz) writel(clk_div, ®s->baudr); } -void rockchip_spi_init(unsigned int bus) +void rockchip_spi_init(unsigned int bus, unsigned int speed_hz) { struct rockchip_spi_slave *espi = &rockchip_spi_slaves[bus]; struct rockchip_spi *regs = espi->regs; @@ -118,7 +114,7 @@ void rockchip_spi_init(unsigned int bus) rkclk_configure_spi(bus, SPI_SRCCLK_HZ); rockchip_spi_enable_chip(regs, 0); - rockchip_spi_set_clk(regs, espi->speed_hz); + rockchip_spi_set_clk(regs, speed_hz); /* Operation Mode */ ctrlr0 = (SPI_OMOD_MASTER << SPI_OMOD_OFFSET); diff --git a/src/soc/rockchip/rk3288/spi.h b/src/soc/rockchip/rk3288/spi.h index c6880c2b23..bba38ef075 100644 --- a/src/soc/rockchip/rk3288/spi.h +++ b/src/soc/rockchip/rk3288/spi.h @@ -199,6 +199,6 @@ check_member(rockchip_spi, rxdr, 0x800); int initialize_rockchip_spi_cbfs_media(struct cbfs_media *media, void *buffer_address, size_t buffer_size); -void rockchip_spi_init(unsigned int bus); +void rockchip_spi_init(unsigned int bus, unsigned int speed_hz); #endif |