diff options
| author | MAULIK V VAGHELA <maulik.v.vaghela@intel.com> | 2021-08-06 18:52:25 +0530 |
|---|---|---|
| committer | Nick Vaccaro <nvaccaro@google.com> | 2021-08-10 21:19:38 +0000 |
| commit | b2513faab2ebf48214d6d9669b85760650b96f83 (patch) | |
| tree | 969aefe87b5b4f4fdebd80baf507403ea7cad1ee | |
| parent | 563a6cc6f2690f2594df51d8d16b3e9f4ef5ca8d (diff) | |
mb/*/{brya,adlrvp}: move cpu_cluster static configuration to chipset.cb
For mainboard devicetree, it always have definition for enabling
cpu_cluster 0 which is required for all the variants.
Since it is SoC related settings, it's better to keep in chipset.cb
as a common setting for all the mainboards using the same SoC.
BUG=None
BRANCH=None
TEST=Change has no functional impact on the brya board.
Change-Id: I8f7c3184b62f8d84ca4605fb9f2a1cc569f1f964
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56853
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
5 files changed, 2 insertions, 8 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb index 162796159e..eb85cb5323 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/alderlake - device cpu_cluster 0 on end - # GPE configuration register "pmc_gpe0_dw0" = "GPP_A" register "pmc_gpe0_dw1" = "GPP_E" diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index 3591a7b29b..8a779bca05 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/alderlake - device cpu_cluster 0 on end - register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" # GPE configuration diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index f4852b920f..d4a2eb72cf 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/alderlake - device cpu_cluster 0 on end - # GPE configuration # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index 3669c86243..b28f387e2b 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -6,8 +6,6 @@ fw_config end chip soc/intel/alderlake - device cpu_cluster 0 on end - # GPE configuration # Note that GPE events called out in ASL code rely on this # route. i.e. If this route changes then the affected GPE diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index 532ec38395..2d5c54e4ae 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -1,5 +1,7 @@ chip soc/intel/alderlake + device cpu_cluster 0 on end + register "power_limits_config[ADL_P_POWER_LIMITS_282_CORE]" = "{ .tdp_pl1_override = 15, .tdp_pl2_override = 55, |