diff options
| author | Nico Huber <nico.huber@secunet.com> | 2023-05-10 18:06:27 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-06-01 13:11:33 +0000 |
| commit | ae81497cb6c7a7d1c4dde837cb84a196752c57bf (patch) | |
| tree | 04ff098549df3f0161eeec2445d7db1556ed7129 | |
| parent | e811c9a44d04bec211f111f73e47f4d3be9d2117 (diff) | |
device/pci: Limit default domain memory window
When the default pci_domain_read_resources() is used,
keep 32-bit memory resources below the limit given by
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT. This serves as a
workaround for missing/wrong reservations of chipset
resources.
This will help to get more stable results from our own
allocator, but is far from a complete solution. Indvi-
dual platform ASL code also needs to be considered, so
the OS won't assign conflicting resources.
Most platforms have reserved space between 0xfe000000
and the 4G barrier. So use that as a global default.
In case of `soc/intel/common/`, use 0xe0000000 because
this is what is advertised in ACPI and there are traces
of resources below 0xfe000000 that are unknown to core-
boot's C code (PCH_PRESERVED_BASE?).
Tested on QEMU/Q35 and Siemens/Chili w/ and w/o top-
down allocation. Fixes EHCI w/ top-down in QEMU.
Change-Id: Iae0d888eebd0ec11a9d6f12975ae24dc32a80d8c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75102
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/device/Kconfig | 9 | ||||
| -rw-r--r-- | src/device/pci_device.c | 17 | ||||
| -rw-r--r-- | src/soc/intel/common/block/systemagent/Kconfig | 3 |
3 files changed, 28 insertions, 1 deletions
diff --git a/src/device/Kconfig b/src/device/Kconfig index 71292e8f15..9c9ecd1973 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -531,6 +531,15 @@ config PCI if PCI +config DOMAIN_RESOURCE_32BIT_LIMIT + hex + default 0xfe000000 + help + When the default pci_domain_read_resources() is used, + keep 32-bit memory resources below this limit. This is + used as a workaround for missing/wrong reservations of + chipset resources that usually reside above this limit. + config NO_ECAM_MMCONF_SUPPORT bool default n diff --git a/src/device/pci_device.c b/src/device/pci_device.c index e600f34fe6..5c5a5fb8dc 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -7,6 +7,7 @@ #include <acpi/acpi.h> #include <assert.h> +#include <cbmem.h> #include <device/pci_ops.h> #include <bootmode.h> #include <console/console.h> @@ -561,8 +562,22 @@ void pci_domain_read_resources(struct device *dev) res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - /* Initialize the system-wide memory resources constraints. */ + /* + * Initialize 32-bit memory resource constraints. + * + * There are often undeclared chipset resources in lower memory + * and memory right below the 4G barrier. Hence, only allow + * one big range from cbmem_top to the configured limit. + */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + res->base = (uintptr_t)cbmem_top(); + res->limit = CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT - 1; + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED; + + /* Initialize 64-bit memory resource constraints above 4G. */ + res = new_resource(dev, IOINDEX_SUBTRACTIVE(2, 0)); + res->base = 4ULL * GiB; res->limit = (1ULL << cpu_phys_address_size()) - 1; res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; diff --git a/src/soc/intel/common/block/systemagent/Kconfig b/src/soc/intel/common/block/systemagent/Kconfig index d8c217f25a..4d14fc127e 100644 --- a/src/soc/intel/common/block/systemagent/Kconfig +++ b/src/soc/intel/common/block/systemagent/Kconfig @@ -6,6 +6,9 @@ config SOC_INTEL_COMMON_BLOCK_SA if SOC_INTEL_COMMON_BLOCK_SA +config DOMAIN_RESOURCE_32BIT_LIMIT + default 0xe0000000 + config ECAM_MMCONF_BASE_ADDRESS default 0xe0000000 |