diff options
| author | V Sowmya <v.sowmya@intel.com> | 2020-12-02 12:00:48 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-12-09 08:22:16 +0000 |
| commit | a6051440e24b9af2935ec1dda95d373e69ac1a72 (patch) | |
| tree | d61cd5533941320d105fb89cbbb16db6ab7285d7 | |
| parent | 2082196e95ea6cb0288fd376e9350e4c969dd5f0 (diff) | |
mb/intel/adlrvp: Add PMC.MUX.CONx device config for Conn2
This patch adds the PMC MUX and CONx devices for adlrvp for
conn2.
BUG=b:170607415
TEST=Built and booted adlrvp. Verified the PMC.MUX CONx objects
in SSDT tables.
Change-Id: I52afbd429750cfa416f4ed93aeb1be590f8c3a5c
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48230
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb index 8033d3d1d3..9130a126a1 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb @@ -3,9 +3,10 @@ chip soc/intel/alderlake device domain 0 on device pci 1f.0 on chip ec/google/chromeec - device pnp 0c09.0 on end use conn0 as mux_conn[0] use conn1 as mux_conn[1] + use conn2 as mux_conn[2] + device pnp 0c09.0 on end end end # eSPI device pci 1f.2 hidden @@ -27,6 +28,13 @@ chip soc/intel/alderlake register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" device generic 1 alias conn1 on end end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "3" + register "usb3_port_number" = "3" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 2 alias conn2 on end + end end end end # PMC |