mb/google/brya: Move gpio_pm settings for brya variants to baseboards

The factory versions (minor version 22) of cr50 FW have an issue with
producing short interrupt pulses, which can be missed by the ADL PCH
if autonomous GPIO power management is enabled, therefore instead of
continually adding the setting to all the variants, move it to the
baseboard instead.

Change-Id: I337f1e9e8f958c02bb73e6701a06c0b88a4757d7
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>

15 files changed, 20 insertions, 134 deletions

diff --git a/src/mainboard/google/brya/variants/anahera/overridetree.cb b/src/mainboard/google/brya/variants/anahera/overridetree.cb
index f2d863a8fd..c9b3bd8045 100644
--- a/src/mainboard/google/brya/variants/anahera/overridetree.cb
+++ b/src/mainboard/google/brya/variants/anahera/overridetree.cb
@@ -22,17 +22,6 @@ fw_config
 	end
 end
 chip soc/intel/alderlake
-	# This disables autonomous GPIO power management, otherwise
-	# old cr50 FW only supports short pulses; need to clarify
-	# the minimum PCH IRQ pulse width with Intel, b/180111628
-	register "gpio_override_pm" = "1"
-	register "gpio_pm[COMM_0]" = "0"
-	register "gpio_pm[COMM_1]" = "0"
-	register "gpio_pm[COMM_2]" = "0"
-	register "gpio_pm[COMM_3]" = "0"
-	register "gpio_pm[COMM_4]" = "0"
-	register "gpio_pm[COMM_5]" = "0"
-
 	register "SaGv" = "SaGv_Enabled"
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
diff --git a/src/mainboard/google/brya/variants/anahera4es/overridetree.cb b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb
index 616224d09e..0b6db9f95e 100644
--- a/src/mainboard/google/brya/variants/anahera4es/overridetree.cb
+++ b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb
@@ -22,17 +22,6 @@ fw_config
 	end
 end
 chip soc/intel/alderlake
-	# This disables autonomous GPIO power management, otherwise
-	# old cr50 FW only supports short pulses; need to clarify
-	# the minimum PCH IRQ pulse width with Intel, b/180111628
-	register "gpio_override_pm" = "1"
-	register "gpio_pm[COMM_0]" = "0"
-	register "gpio_pm[COMM_1]" = "0"
-	register "gpio_pm[COMM_2]" = "0"
-	register "gpio_pm[COMM_3]" = "0"
-	register "gpio_pm[COMM_4]" = "0"
-	register "gpio_pm[COMM_5]" = "0"
-
 	register "SaGv" = "SaGv_Enabled"
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
index d9a4e42c04..a7328a9bbe 100644
--- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
@@ -71,6 +71,16 @@ chip soc/intel/alderlake
         # FIVR RFI Spread Spectrum 1.5%
         register "FivrSpreadSpectrum" = "FIVR_SS_1_5"
 
+	# This disables autonomous GPIO power management, otherwise
+	# old cr50 FW only supports short pulses.
+	register "gpio_override_pm" = "1"
+	register "gpio_pm[COMM_0]" = "0"
+	register "gpio_pm[COMM_1]" = "0"
+	register "gpio_pm[COMM_2]" = "0"
+	register "gpio_pm[COMM_3]" = "0"
+	register "gpio_pm[COMM_4]" = "0"
+	register "gpio_pm[COMM_5]" = "0"
+
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
 	#| Field             |  Value                    |
diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
index b330e98040..7323b106c7 100644
--- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
@@ -75,6 +75,16 @@ chip soc/intel/alderlake
 	# FIVR RFI Spread Spectrum 1.5%
 	register "FivrSpreadSpectrum" = "FIVR_SS_1_5"
 
+	# This disables autonomous GPIO power management, otherwise old cr50 FW
+	# only supports short pulses and they can be missed by the PCH.
+	register "gpio_override_pm" = "1"
+	register "gpio_pm[COMM_0]" = "0"
+	register "gpio_pm[COMM_1]" = "0"
+	register "gpio_pm[COMM_2]" = "0"
+	register "gpio_pm[COMM_3]" = "0"
+	register "gpio_pm[COMM_4]" = "0"
+	register "gpio_pm[COMM_5]" = "0"
+
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
 	#| Field             |  Value                    |
diff --git a/src/mainboard/google/brya/variants/brask/overridetree.cb b/src/mainboard/google/brya/variants/brask/overridetree.cb
index b7e9fef7ae..d60183bcb7 100644
--- a/src/mainboard/google/brya/variants/brask/overridetree.cb
+++ b/src/mainboard/google/brya/variants/brask/overridetree.cb
@@ -1,14 +1,4 @@
 chip soc/intel/alderlake
-	# This disables autonomous GPIO power management, otherwise
-	# old cr50 FW only supports short pulses; need to clarify
-	# the minimum PCH IRQ pulse width with Intel, b/180111628
-	register "gpio_override_pm" = "1"
-	register "gpio_pm[COMM_0]" = "0"
-	register "gpio_pm[COMM_1]" = "0"
-	register "gpio_pm[COMM_2]" = "0"
-	register "gpio_pm[COMM_3]" = "0"
-	register "gpio_pm[COMM_4]" = "0"
-	register "gpio_pm[COMM_5]" = "0"
 	device domain 0 on
 		device ref dtt on
 			chip drivers/intel/dptf
diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb
index 91ae8005f9..401909b43f 100644
--- a/src/mainboard/google/brya/variants/gimble/overridetree.cb
+++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb
@@ -21,16 +21,6 @@ fw_config
 	end
 end
 chip soc/intel/alderlake
-	# This disabled autonomous GPIO power management, otherwise
-	# old cr50 FW only supports short pulses; need to clarify
-	# the minimum PCH IRQ pulse width with Intel, b/180111628
-	register "gpio_override_pm" = "1"
-	register "gpio_pm[COMM_0]" = "0"
-	register "gpio_pm[COMM_1]" = "0"
-	register "gpio_pm[COMM_2]" = "0"
-	register "gpio_pm[COMM_3]" = "0"
-	register "gpio_pm[COMM_4]" = "0"
-	register "gpio_pm[COMM_5]" = "0"
 	register "SaGv" = "SaGv_Enabled"
 	register "PsysPmax" = "143"
 	register "TcssAuxOri" = "1"
diff --git a/src/mainboard/google/brya/variants/gimble4es/overridetree.cb b/src/mainboard/google/brya/variants/gimble4es/overridetree.cb
index 5b022f642c..0b29e4d02d 100644
--- a/src/mainboard/google/brya/variants/gimble4es/overridetree.cb
+++ b/src/mainboard/google/brya/variants/gimble4es/overridetree.cb
@@ -21,16 +21,6 @@ fw_config
 	end
 end
 chip soc/intel/alderlake
-	# This disabled autonomous GPIO power management, otherwise
-	# old cr50 FW only supports short pulses; need to clarify
-	# the minimum PCH IRQ pulse width with Intel, b/180111628
-	register "gpio_override_pm" = "1"
-	register "gpio_pm[COMM_0]" = "0"
-	register "gpio_pm[COMM_1]" = "0"
-	register "gpio_pm[COMM_2]" = "0"
-	register "gpio_pm[COMM_3]" = "0"
-	register "gpio_pm[COMM_4]" = "0"
-	register "gpio_pm[COMM_5]" = "0"
 	register "SaGv" = "SaGv_Enabled"
 	register "PsysPmax" = "143"
 	register "TcssAuxOri" = "1"
diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb
index 7ef832cc5d..a12de65622 100644
--- a/src/mainboard/google/brya/variants/primus/overridetree.cb
+++ b/src/mainboard/google/brya/variants/primus/overridetree.cb
@@ -23,16 +23,6 @@ fw_config
 end
 
 chip soc/intel/alderlake
-	# This disabled autonomous GPIO power management, otherwise
-	# old cr50 FW only supports short pulses; need to clarify
-	# the minimum PCH IRQ pulse width with Intel, b/180111628
-	register "gpio_override_pm" = "1"
-	register "gpio_pm[COMM_0]" = "0"
-	register "gpio_pm[COMM_1]" = "0"
-	register "gpio_pm[COMM_2]" = "0"
-	register "gpio_pm[COMM_3]" = "0"
-	register "gpio_pm[COMM_4]" = "0"
-	register "gpio_pm[COMM_5]" = "0"
 	register "SaGv" = "SaGv_Enabled"
 	register "MaxDramSpeed" = "3733"
 	# Acoustic settings
diff --git a/src/mainboard/google/brya/variants/primus4es/overridetree.cb b/src/mainboard/google/brya/variants/primus4es/overridetree.cb
index 75610b87b2..dc0dfbfb22 100644
--- a/src/mainboard/google/brya/variants/primus4es/overridetree.cb
+++ b/src/mainboard/google/brya/variants/primus4es/overridetree.cb
@@ -23,16 +23,6 @@ fw_config
 end
 
 chip soc/intel/alderlake
-	# This disabled autonomous GPIO power management, otherwise
-	# old cr50 FW only supports short pulses; need to clarify
-	# the minimum PCH IRQ pulse width with Intel, b/180111628
-	register "gpio_override_pm" = "1"
-	register "gpio_pm[COMM_0]" = "0"
-	register "gpio_pm[COMM_1]" = "0"
-	register "gpio_pm[COMM_2]" = "0"
-	register "gpio_pm[COMM_3]" = "0"
-	register "gpio_pm[COMM_4]" = "0"
-	register "gpio_pm[COMM_5]" = "0"
 	register "SaGv" = "SaGv_Enabled"
 	register "MaxDramSpeed" = "3733"
 	# Acoustic settings
diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb
index 013ec09d71..a94f33325b 100644
--- a/src/mainboard/google/brya/variants/redrix/overridetree.cb
+++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb
@@ -31,16 +31,6 @@ fw_config
 	end
 end
 chip soc/intel/alderlake
-	# This disables autonomous GPIO power management, otherwise
-	# old cr50 FW only supports short pulses; need to clarify
-	# the minimum PCH IRQ pulse width with Intel, b/180111628
-	register "gpio_override_pm" = "1"
-	register "gpio_pm[COMM_0]" = "0"
-	register "gpio_pm[COMM_1]" = "0"
-	register "gpio_pm[COMM_2]" = "0"
-	register "gpio_pm[COMM_3]" = "0"
-	register "gpio_pm[COMM_4]" = "0"
-	register "gpio_pm[COMM_5]" = "0"
 	register "SaGv" = "SaGv_Enabled"
 	register "CnviBtAudioOffload" = "true"
 	# FIVR RFI Spread Spectrum 6%
diff --git a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb
index a31d025897..0abad3d7f1 100644
--- a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb
+++ b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb
@@ -31,16 +31,6 @@ fw_config
 	end
 end
 chip soc/intel/alderlake
-	# This disables autonomous GPIO power management, otherwise
-	# old cr50 FW only supports short pulses; need to clarify
-	# the minimum PCH IRQ pulse width with Intel, b/180111628
-	register "gpio_override_pm" = "1"
-	register "gpio_pm[COMM_0]" = "0"
-	register "gpio_pm[COMM_1]" = "0"
-	register "gpio_pm[COMM_2]" = "0"
-	register "gpio_pm[COMM_3]" = "0"
-	register "gpio_pm[COMM_4]" = "0"
-	register "gpio_pm[COMM_5]" = "0"
 	register "SaGv" = "SaGv_Enabled"
 	register "CnviBtAudioOffload" = "true"
 	# FIVR RFI Spread Spectrum 6%
diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb
index 5cdc066dbf..c1c567e7fa 100644
--- a/src/mainboard/google/brya/variants/taeko/overridetree.cb
+++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb
@@ -39,16 +39,6 @@ fw_config
 	end
 end
 chip soc/intel/alderlake
-	# This disabled autonomous GPIO power management, otherwise
-	# old cr50 FW only supports short pulses; need to clarify
-	# the minimum PCH IRQ pulse width with Intel, b/180111628
-	register "gpio_override_pm" = "1"
-	register "gpio_pm[COMM_0]" = "0"
-	register "gpio_pm[COMM_1]" = "0"
-	register "gpio_pm[COMM_2]" = "0"
-	register "gpio_pm[COMM_3]" = "0"
-	register "gpio_pm[COMM_4]" = "0"
-	register "gpio_pm[COMM_5]" = "0"
 	register "ext_fivr_settings" = "{
 		.configure_ext_fivr = 1,
 		.v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX,
diff --git a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb
index 8aaeab7b71..5b7b49708e 100644
--- a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb
+++ b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb
@@ -39,16 +39,6 @@ fw_config
 	end
 end
 chip soc/intel/alderlake
-	# This disabled autonomous GPIO power management, otherwise
-	# old cr50 FW only supports short pulses; need to clarify
-	# the minimum PCH IRQ pulse width with Intel, b/180111628
-	register "gpio_override_pm" = "1"
-	register "gpio_pm[COMM_0]" = "0"
-	register "gpio_pm[COMM_1]" = "0"
-	register "gpio_pm[COMM_2]" = "0"
-	register "gpio_pm[COMM_3]" = "0"
-	register "gpio_pm[COMM_4]" = "0"
-	register "gpio_pm[COMM_5]" = "0"
 	register "ext_fivr_settings" = "{
 		.configure_ext_fivr = 1,
 		.v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX,
diff --git a/src/mainboard/google/brya/variants/taniks/overridetree.cb b/src/mainboard/google/brya/variants/taniks/overridetree.cb
index eb1680e0dc..4b97a48b44 100644
--- a/src/mainboard/google/brya/variants/taniks/overridetree.cb
+++ b/src/mainboard/google/brya/variants/taniks/overridetree.cb
@@ -36,16 +36,6 @@ fw_config
 	end
 end
 chip soc/intel/alderlake
-	# This disabled autonomous GPIO power management, otherwise
-	# old cr50 FW only supports short pulses; need to clarify
-	# the minimum PCH IRQ pulse width with Intel, b/180111628
-	register "gpio_override_pm" = "1"
-	register "gpio_pm[COMM_0]" = "0"
-	register "gpio_pm[COMM_1]" = "0"
-	register "gpio_pm[COMM_2]" = "0"
-	register "gpio_pm[COMM_3]" = "0"
-	register "gpio_pm[COMM_4]" = "0"
-	register "gpio_pm[COMM_5]" = "0"
 	register "ext_fivr_settings" = "{
 		.configure_ext_fivr = 1,
 		.v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX,
diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb
index fe929b5fd3..034d496bb9 100644
--- a/src/mainboard/google/brya/variants/vell/overridetree.cb
+++ b/src/mainboard/google/brya/variants/vell/overridetree.cb
@@ -22,18 +22,6 @@ fw_config
 	end
 end
 chip soc/intel/alderlake
-	# This disables autonomous GPIO power management, otherwise
-	# old cr50 FW only supports short pulses; need to clarify
-	# the minimum PCH IRQ pulse width with Intel, b/180111628
-	register "gpio_override_pm" = "1"
-	register "gpio_pm[COMM_0]" = "0"
-	register "gpio_pm[COMM_1]" = "0"
-	register "gpio_pm[COMM_2]" = "0"
-	register "gpio_pm[COMM_3]" = "0"
-	register "gpio_pm[COMM_4]" = "0"
-	register "gpio_pm[COMM_5]" = "0"
-	register "SaGv" = "SaGv_Enabled"
-
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
 	#| Field             |  Value                    |