soc/intel/{skl,cnl}: replace PM ACPI timer dt option by Kconfig

Select `PM_ACPI_TIMER_OPTIONAL` to enable the new PM ACPI Kconfig and
set the FSP option for PM ACPI timer enablement from its value instead
of using the old devicetree option.

Also drop the obsolete devicetree option from soc code and from the
mainboards and add a corresponding Kconfig entry instead.

Change-Id: I10724ccf1647594404cec15c2349ab05b6c9714f
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45955
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

40 files changed, 41 insertions, 34 deletions

diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb
index 561bd6f54b..49e2964f45 100644
--- a/src/mainboard/51nb/x210/devicetree.cb
+++ b/src/mainboard/51nb/x210/devicetree.cb
@@ -55,7 +55,6 @@ chip soc/intel/skylake
 	register "PmConfigSlpS4MinAssert" = "1"		# 1s
 	register "PmConfigSlpSusMinAssert" = "3"	# 500ms
 	register "PmConfigSlpAMinAssert" = "3"		# 2s
-	register "PmTimerDisabled" = "0"
 
 	register "serirq_mode" = "SERIRQ_CONTINUOUS"
 
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb
index 57acd33570..909c050412 100644
--- a/src/mainboard/asrock/h110m/devicetree.cb
+++ b/src/mainboard/asrock/h110m/devicetree.cb
@@ -24,7 +24,6 @@ chip soc/intel/skylake
 	# FSP Configuration
 	register "PrimaryDisplay" = "Display_PEG"
 	register "SaGv" = "SaGv_Enabled"
-	register "PmTimerDisabled" = "0"
 
 	# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
 	# SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
diff --git a/src/mainboard/facebook/monolith/Kconfig b/src/mainboard/facebook/monolith/Kconfig
index 92c02a799e..ddbc27ef91 100644
--- a/src/mainboard/facebook/monolith/Kconfig
+++ b/src/mainboard/facebook/monolith/Kconfig
@@ -92,4 +92,7 @@ config VBOOT_ALWAYS_ALLOW_UDC
 	def_bool y
 	depends on VBOOT && !CHROMEOS
 
+config USE_PM_ACPI_TIMER
+	default n
+
 endif
diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb
index 15ab7efb71..974d00e41a 100644
--- a/src/mainboard/facebook/monolith/devicetree.cb
+++ b/src/mainboard/facebook/monolith/devicetree.cb
@@ -36,7 +36,6 @@ chip soc/intel/skylake
 	register "ScsEmmcHs400Enabled" = "1"
 	register "SkipExtGfxScan" = "1"
 	register "SaGv" = "SaGv_Enabled"
-	register "PmTimerDisabled" = "1"
 	register "HeciEnabled" = "0"
 
 	register "SataSalpSupport" = "1"
diff --git a/src/mainboard/google/eve/Kconfig b/src/mainboard/google/eve/Kconfig
index f7e82959ce..9316c7f213 100644
--- a/src/mainboard/google/eve/Kconfig
+++ b/src/mainboard/google/eve/Kconfig
@@ -76,4 +76,7 @@ config INCLUDE_NHLT_BLOBS
 config UART_FOR_CONSOLE
 	int
 	default 2
+
+config USE_PM_ACPI_TIMER
+	default n
 endif
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb
index 519e53ba6c..6c1144b736 100644
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -51,7 +51,6 @@ chip soc/intel/skylake
 	register "PmConfigSlpS4MinAssert" = "1"        # 1s
 	register "PmConfigSlpSusMinAssert" = "1"       # 500ms
 	register "PmConfigSlpAMinAssert" = "3"         # 2s
-	register "PmTimerDisabled" = "1"
 
 	# VR Settings Configuration for 4 Domains
 	#+----------------+-------+-------+-------+-------+
diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig
index 48d04e791b..a21df378ef 100644
--- a/src/mainboard/google/fizz/Kconfig
+++ b/src/mainboard/google/fizz/Kconfig
@@ -96,4 +96,8 @@ config INCLUDE_NHLT_BLOBS_KARMA
 config UART_FOR_CONSOLE
 	int
 	default 2
+
+config USE_PM_ACPI_TIMER
+	default n
+
 endif # BOARD_GOOGLE_BASEBOARD_FIZZ
diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
index 703ef5b775..22935f4520 100644
--- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
@@ -82,7 +82,6 @@ chip soc/intel/skylake
 	register "PmConfigSlpS4MinAssert" = "1"        # 1s
 	register "PmConfigSlpSusMinAssert" = "1"       # 500ms
 	register "PmConfigSlpAMinAssert" = "3"         # 2s
-	register "PmTimerDisabled" = "1"
 	register "SendVrMbxCmd" = "1"                  # IMVP8 workaround
 
 	# Intersil VR c-state issue workaround
diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig
index 50e56ce9e7..144fe97b8b 100644
--- a/src/mainboard/google/glados/Kconfig
+++ b/src/mainboard/google/glados/Kconfig
@@ -86,4 +86,7 @@ config CONSOLE_SERIAL
 	bool
 	default n
 
+config USE_PM_ACPI_TIMER
+	default n
+
 endif
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index 2dfb71f2c0..ba3f204d09 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -50,7 +50,6 @@ chip soc/intel/skylake
 	register "PmConfigSlpS4MinAssert" = "4"        # 4s
 	register "PmConfigSlpSusMinAssert" = "3"       # 4s
 	register "PmConfigSlpAMinAssert" = "3"         # 2s
-	register "PmTimerDisabled" = "1"
 
 	# Enable Root port 1
 	register "PcieRpEnable[0]" = "1"
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig
index 1e132ed0fd..4d7d5ec990 100644
--- a/src/mainboard/google/hatch/Kconfig
+++ b/src/mainboard/google/hatch/Kconfig
@@ -186,4 +186,7 @@ config VBOOT
 	select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
 	select VBOOT_EARLY_EC_SYNC
 
+config USE_PM_ACPI_TIMER
+	default n
+
 endif # BOARD_GOOGLE_HATCH_COMMON
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
index 01c0d234f9..31f6652401 100644
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -53,8 +53,6 @@ chip soc/intel/cannonlake
 	# putting it under register "common_soc_config" in overridetree.cb file.
 	register "common_soc_config.pch_thermal_trip" = "77"
 
-	register "PmTimerDisabled" = "1"
-
 	# Select CPU PL2/PL4 config
 	register "cpu_pl2_4_cfg" = "baseline"
 
diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig
index bda2ca0a18..d8b90bcdc3 100644
--- a/src/mainboard/google/poppy/Kconfig
+++ b/src/mainboard/google/poppy/Kconfig
@@ -214,4 +214,8 @@ config VBOOT
 config UART_FOR_CONSOLE
 	int
 	default 2
+
+config USE_PM_ACPI_TIMER
+	default n
+
 endif # BOARD_GOOGLE_BASEBOARD_POPPY
diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
index 668e72dc21..2f230faf3f 100644
--- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
@@ -57,7 +57,6 @@ chip soc/intel/skylake
 	register "PmConfigSlpS4MinAssert" = "1"        # 1s
 	register "PmConfigSlpSusMinAssert" = "1"       # 500ms
 	register "PmConfigSlpAMinAssert" = "3"         # 2s
-	register "PmTimerDisabled" = "1"
 
 	register "power_limits_config" = "{
 		.tdp_pl1_override = 7,
diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
index 0b3d6c0346..ed846f61e2 100644
--- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
@@ -47,7 +47,6 @@ chip soc/intel/skylake
 	register "PmConfigSlpS4MinAssert" = "1"        # 1s
 	register "PmConfigSlpSusMinAssert" = "1"       # 500ms
 	register "PmConfigSlpAMinAssert" = "3"         # 2s
-	register "PmTimerDisabled" = "1"
 
 	# VR Settings Configuration for 4 Domains
 	#+----------------+-------+-------+-------+-------+
diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb
index 42f810800a..5117c545f1 100644
--- a/src/mainboard/google/poppy/variants/nami/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb
@@ -46,7 +46,6 @@ chip soc/intel/skylake
 	register "PmConfigSlpS4MinAssert" = "1"        # 1s
 	register "PmConfigSlpSusMinAssert" = "1"       # 500ms
 	register "PmConfigSlpAMinAssert" = "3"         # 2s
-	register "PmTimerDisabled" = "1"
 
 	# Intersil VR c-state issue workaround
 	# send VR mailbox command for IA/GT/SA rails
diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
index 3d91884d51..b1340f8058 100644
--- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
@@ -47,7 +47,6 @@ chip soc/intel/skylake
 	register "PmConfigSlpS4MinAssert" = "1"        # 1s
 	register "PmConfigSlpSusMinAssert" = "1"       # 500ms
 	register "PmConfigSlpAMinAssert" = "3"         # 2s
-	register "PmTimerDisabled" = "1"
 
 	# VR Slew rate setting for improving audible noise
 	register "AcousticNoiseMitigation" = "1"
diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
index ab1588af80..2d077c29fc 100644
--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
@@ -52,7 +52,6 @@ chip soc/intel/skylake
 	register "PmConfigSlpS4MinAssert" = "1"        # 1s
 	register "PmConfigSlpSusMinAssert" = "1"       # 500ms
 	register "PmConfigSlpAMinAssert" = "3"         # 2s
-	register "PmTimerDisabled" = "1"
 
 	register "power_limits_config" = "{
 		.tdp_pl1_override = 7,
diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
index 2334a179df..2a916fc1df 100644
--- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
@@ -57,7 +57,6 @@ chip soc/intel/skylake
 	register "PmConfigSlpS4MinAssert" = "1"        # 1s
 	register "PmConfigSlpSusMinAssert" = "1"       # 500ms
 	register "PmConfigSlpAMinAssert" = "3"         # 2s
-	register "PmTimerDisabled" = "1"
 
 	# VR Settings Configuration for 4 Domains
 	#+----------------+-------+-------+-------+-------+
diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
index c69875597d..a3ee45c809 100644
--- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
@@ -47,7 +47,6 @@ chip soc/intel/skylake
 	register "PmConfigSlpS4MinAssert" = "1"        # 1s
 	register "PmConfigSlpSusMinAssert" = "1"       # 500ms
 	register "PmConfigSlpAMinAssert" = "3"         # 2s
-	register "PmTimerDisabled" = "1"
 
 	# VR Settings Configuration for 4 Domains
 	#+----------------+-------+-------+-------+-------+
diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig
index f1db3dac3f..5dccdaed93 100644
--- a/src/mainboard/intel/kblrvp/Kconfig
+++ b/src/mainboard/intel/kblrvp/Kconfig
@@ -84,4 +84,9 @@ config DIMM_SPD_SIZE
 config UART_FOR_CONSOLE
 	int
 	default 2
+
+config USE_PM_ACPI_TIMER
+	default n if BOARD_INTEL_KBLRVP3
+	default n if BOARD_INTEL_KBLRVP7
+
 endif
diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
index fbf08cde3f..782f3dc524 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
@@ -3,7 +3,6 @@ chip soc/intel/skylake
 	# FSP Configuration
 	register "DspEnable" = "0"
 	register "ScsEmmcHs400Enabled" = "0"
-	register "PmTimerDisabled" = "0"
 
 	register "serirq_mode" = "SERIRQ_CONTINUOUS"
 
diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
index 0754c0735e..397155b789 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
@@ -8,7 +8,6 @@ chip soc/intel/skylake
 
 	# FSP Configuration
 	register "DspEnable" = "1"
-	register "PmTimerDisabled" = "1"
 
 	# VR Settings Configuration for 4 Domains
 	#+----------------+-------+-------+-------+-------+
diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb
index 11f9c01501..e649ed72e7 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb
@@ -12,9 +12,6 @@ chip soc/intel/skylake
 	# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
 	register "gen2_dec" = "0x000c0201"
 
-	# FSP Configuration
-	register "PmTimerDisabled" = "1"
-
 	# VR Settings Configuration for 4 Domains
 	#+----------------+-------+-------+-------+-------+
 	#| Domain/Setting |  SA   |  IA   | GTUS  |  GTS  |
diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
index 78552fcdd5..115e338199 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
@@ -6,7 +6,6 @@ chip soc/intel/skylake
 
 	# FSP Configuration
 	register "ScsEmmcHs400Enabled" = "0"
-	register "PmTimerDisabled" = "0"
 
 	register "serirq_mode" = "SERIRQ_CONTINUOUS"
 
diff --git a/src/mainboard/intel/kunimitsu/Kconfig b/src/mainboard/intel/kunimitsu/Kconfig
index 6e745d947a..b9b7d5a394 100644
--- a/src/mainboard/intel/kunimitsu/Kconfig
+++ b/src/mainboard/intel/kunimitsu/Kconfig
@@ -60,4 +60,8 @@ config INCLUDE_NHLT_BLOBS
 config UART_FOR_CONSOLE
 	int
 	default 2
+
+config USE_PM_ACPI_TIMER
+	default n
+
 endif
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index 07afb7bd1b..85586cb137 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -27,7 +27,6 @@ chip soc/intel/skylake
 	register "SkipExtGfxScan" = "1"
 	register "HeciEnabled" = "0"
 	register "SaGv" = "SaGv_Enabled"
-	register "PmTimerDisabled" = "1"
 
 	# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
 	# SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb
index 5c64326e3e..0da097fa4a 100644
--- a/src/mainboard/intel/saddlebrook/devicetree.cb
+++ b/src/mainboard/intel/saddlebrook/devicetree.cb
@@ -21,7 +21,6 @@ chip soc/intel/skylake
 	register "SkipExtGfxScan" = "1"
 
 	register "SaGv" = "SaGv_Enabled"
-	register "PmTimerDisabled" = "0"
 
 	# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
 	# SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
diff --git a/src/mainboard/libretrend/lt1000/Kconfig b/src/mainboard/libretrend/lt1000/Kconfig
index 9c4223ae4b..bfd532a85a 100644
--- a/src/mainboard/libretrend/lt1000/Kconfig
+++ b/src/mainboard/libretrend/lt1000/Kconfig
@@ -44,4 +44,7 @@ config CBFS_SIZE
 	hex
 	default 0x600000
 
+config USE_PM_ACPI_TIMER
+	default n
+
 endif
diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb
index 911690f053..f6e73c6bd6 100644
--- a/src/mainboard/libretrend/lt1000/devicetree.cb
+++ b/src/mainboard/libretrend/lt1000/devicetree.cb
@@ -55,7 +55,6 @@ chip soc/intel/skylake
 	register "PmConfigSlpS4MinAssert" = "1"        # 1s
 	register "PmConfigSlpSusMinAssert" = "3"       # 500ms
 	register "PmConfigSlpAMinAssert" = "3"         # 2s
-	register "PmTimerDisabled" = "1"
 
 	# VR Settings Configuration for 4 Domains
 	#+----------------+-------+-------+-------------+-------+
diff --git a/src/mainboard/protectli/vault_kbl/Kconfig b/src/mainboard/protectli/vault_kbl/Kconfig
index 518bb6dca5..7cf80e0a91 100644
--- a/src/mainboard/protectli/vault_kbl/Kconfig
+++ b/src/mainboard/protectli/vault_kbl/Kconfig
@@ -51,4 +51,7 @@ config CBFS_SIZE
 	hex
 	default 0x600000
 
+config USE_PM_ACPI_TIMER
+	default n
+
 endif
diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb
index e6e748a247..d8e68a2373 100644
--- a/src/mainboard/protectli/vault_kbl/devicetree.cb
+++ b/src/mainboard/protectli/vault_kbl/devicetree.cb
@@ -40,7 +40,6 @@ chip soc/intel/skylake
 	register "ScsEmmcHs400Enabled" = "0"
 	register "SkipExtGfxScan" = "1"
 	register "HeciEnabled" = "1"
-	register "PmTimerDisabled" = "1"
 	register "SaGv" = "SaGv_Enabled"
 	register "IslVrCmd" = "2"
 	register "PmConfigSlpS3MinAssert" = "2"		# 50ms
diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb
index 2c73280148..b796fbbc9c 100644
--- a/src/mainboard/purism/librem_skl/devicetree.cb
+++ b/src/mainboard/purism/librem_skl/devicetree.cb
@@ -61,7 +61,6 @@ chip soc/intel/skylake
 	register "PmConfigSlpS4MinAssert" = "1"		# 1s
 	register "PmConfigSlpSusMinAssert" = "3"	# 500ms
 	register "PmConfigSlpAMinAssert" = "3"		# 2s
-	register "PmTimerDisabled" = "0"
 
 	# EC/KBC requires continuous mode
 	register "serirq_mode" = "SERIRQ_CONTINUOUS"
diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
index 4f8ceb6815..15ea78538e 100644
--- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
+++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
@@ -41,7 +41,6 @@ chip soc/intel/skylake
 	register "PmConfigSlpS4MinAssert" = "1"		# 1s
 	register "PmConfigSlpSusMinAssert" = "3"	# 500ms
 	register "PmConfigSlpAMinAssert" = "3"		# 2s
-	register "PmTimerDisabled" = "0"
 
 	register "serirq_mode" = "SERIRQ_CONTINUOUS"
 
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index d61435aaa6..7b9b88be61 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -97,6 +97,7 @@ config CPU_SPECIFIC_OPTIONS
 	select PARALLEL_MP_AP_WORK
 	select PLATFORM_USES_FSP2_0
 	select REG_SCRIPT
+	select PM_ACPI_TIMER_OPTIONAL
 	select PMC_GLOBAL_RESET_ENABLE_LOCK
 	select SOC_INTEL_COMMON
 	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index dc24e9bd8f..2a52627be7 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -273,8 +273,6 @@ struct soc_intel_cannonlake_config {
 	/* Enable C6 DRAM */
 	uint8_t enable_c6dram;
 
-	uint8_t PmTimerDisabled;
-
 	/*
 	 * SLP_S3 Minimum Assertion Width Policy
 	 *  1 = 60us
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index fe7641f27b..9b28d3d795 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -248,6 +248,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER);
 	params->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER);
 
+	params->EnableTcoTimer = CONFIG(USE_PM_ACPI_TIMER);
+
 	/* USB */
 	for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
 		params->PortUsb20Enable[i] = config->usb2_ports[i].enable;
@@ -432,9 +434,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	params->FastPkgCRampDisableSa = config->FastPkgCRampDisableSa;
 	params->FastPkgCRampDisableFivr = config->FastPkgCRampDisableFivr;
 
-	/* Disable PCH ACPI timer */
-	params->EnableTcoTimer = !config->PmTimerDisabled;
-
 	/* Apply minimum assertion width settings if non-zero */
 	if (config->PchPmSlpS3MinAssert)
 		params->PchPmSlpS3MinAssert = config->PchPmSlpS3MinAssert;
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index f71beaed52..ce46d06b03 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -42,6 +42,7 @@ config CPU_SPECIFIC_OPTIONS
 	select PLATFORM_USES_FSP2_0
 	select REG_SCRIPT
 	select SA_ENABLE_DPR
+	select PM_ACPI_TIMER_OPTIONAL
 	select PMC_GLOBAL_RESET_ENABLE_LOCK
 	select SOC_INTEL_COMMON
 	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 1e13428252..e2aee07114 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -235,6 +235,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	/* Legacy 8254 timer support */
 	params->Early8254ClockGatingEnable = !CONFIG(USE_LEGACY_8254_TIMER);
 
+	params->EnableTcoTimer = CONFIG(USE_PM_ACPI_TIMER);
+
 	memcpy(params->SerialIoDevMode, config->SerialIoDevMode,
 	       sizeof(params->SerialIoDevMode));
 
@@ -297,7 +299,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	params->Device4Enable = dev && dev->enabled;
 	dev = pcidev_path_on_root(PCH_DEVFN_THERMAL);
 	params->PchThermalDeviceEnable = dev && dev->enabled;
-	params->EnableTcoTimer = !config->PmTimerDisabled;
 
 	tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi;
 	tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock;
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 41482f10bd..0bab45ab22 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -460,7 +460,6 @@ struct soc_intel_skylake_config {
 	 * Setting to 0 (default) disables Heci1 and hides the device from OS
 	 */
 	u8 HeciEnabled;
-	u8 PmTimerDisabled;
 
 	/*
 	 * Enable VR specific mailbox command