diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2022-06-10 21:04:36 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-06-13 15:53:32 +0000 |
| commit | a05f518dea5fe700d99dcce1882739a15427a0d9 (patch) | |
| tree | 499b3d6d021987e165a61a6429b371942bd1e002 | |
| parent | 868282e195dd8700d0e3d2a26ba7295f21a15f56 (diff) | |
soc/amd/sabrina: only make the available clock outputs configurable
Sabrina only has 4 PCIe clock outputs with corresponding clock request
pins available, so only make those 4 configurable in devicetree and
disable the rest unconditionally.
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5d34fa680dd20a6eec86cc278c1c901b3231df83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
| -rw-r--r-- | src/soc/amd/sabrina/chip.h | 2 | ||||
| -rw-r--r-- | src/soc/amd/sabrina/fch.c | 6 | ||||
| -rw-r--r-- | src/soc/amd/sabrina/include/soc/southbridge.h | 1 |
3 files changed, 6 insertions, 3 deletions
diff --git a/src/soc/amd/sabrina/chip.h b/src/soc/amd/sabrina/chip.h index c272f9f2dc..3662605964 100644 --- a/src/soc/amd/sabrina/chip.h +++ b/src/soc/amd/sabrina/chip.h @@ -90,7 +90,7 @@ struct soc_amd_sabrina_config { GPP_CLK_ON, /* GPP clock always on; default */ GPP_CLK_REQ, /* GPP clock controlled by corresponding #CLK_REQx pin */ GPP_CLK_OFF, /* GPP clk off */ - } gpp_clk_config[GPP_CLK_OUTPUT_COUNT]; + } gpp_clk_config[GPP_CLK_OUTPUT_AVAILABLE]; /* performance policy for the PCIe links: power consumption vs. link speed */ enum { diff --git a/src/soc/amd/sabrina/fch.c b/src/soc/amd/sabrina/fch.c index a768989b64..533eb9489c 100644 --- a/src/soc/amd/sabrina/fch.c +++ b/src/soc/amd/sabrina/fch.c @@ -151,9 +151,11 @@ static void gpp_clk_setup(void) * The remapping of values is done so that the default of the enum used for the * devicetree settings is the clock being enabled, so that a missing devicetree * configuration for this will result in an always active clock and not an - * inactive PCIe clock output. + * inactive PCIe clock output. Only the configuration for the clock outputs + * available on the package is provided via the devicetree; the rest is + * switched off unconditionally. */ - switch (cfg->gpp_clk_config[i]) { + switch (i < GPP_CLK_OUTPUT_AVAILABLE ? cfg->gpp_clk_config[i] : GPP_CLK_OFF) { case GPP_CLK_REQ: gpp_clk_ctl |= GPP_CLK_REQ_EXT(gpp_clk_shift_lut[i]); break; diff --git a/src/soc/amd/sabrina/include/soc/southbridge.h b/src/soc/amd/sabrina/include/soc/southbridge.h index e755d5019c..d72696285d 100644 --- a/src/soc/amd/sabrina/include/soc/southbridge.h +++ b/src/soc/amd/sabrina/include/soc/southbridge.h @@ -96,6 +96,7 @@ #define GPP_CLK5_REQ_SHIFT 10 #define GPP_CLK6_REQ_SHIFT 12 #define GPP_CLK_OUTPUT_COUNT 7 +#define GPP_CLK_OUTPUT_AVAILABLE 4 #define GPP_CLK_REQ_MASK(clk_shift) (0x3 << (clk_shift)) #define GPP_CLK_REQ_ON(clk_shift) (0x3 << (clk_shift)) #define GPP_CLK_REQ_EXT(clk_shift) (0x1 << (clk_shift)) |