diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2023-10-17 11:36:11 -0700 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2024-04-01 04:16:34 +0000 |
| commit | a010b7f614dbdf5155e380c49fd07bc440b5a769 (patch) | |
| tree | 65f030d31f155f2f736833aff09397dc18637fb1 | |
| parent | 347b1170fb86072724194579b27d2cf86a639725 (diff) | |
arch/ppc64: Fix inline assembly for clang
Use macros from the Linux kernel 6.5 to make the inline assembly also
compile on clang.
TEST: See that the generated code is identical on GCC and compiles on
clang.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I516033c69e62dfdb38f83285c156d5527917ad55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
| -rw-r--r-- | src/arch/ppc64/stages.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/arch/ppc64/stages.c b/src/arch/ppc64/stages.c index 01b9efaba8..c6d35ed452 100644 --- a/src/arch/ppc64/stages.c +++ b/src/arch/ppc64/stages.c @@ -25,10 +25,15 @@ void stage_entry(uintptr_t stage_arg) _cbmem_top_ptr = stage_arg; #if ENV_RAMSTAGE +#define __stringify_in_c(...) #__VA_ARGS__ +#define stringify_in_c(...) __stringify_in_c(__VA_ARGS__) " " +#define PPC_RAW_SLBIA(IH) (0x7c0003e4 | (((IH) & 0x7) << 21)) +#define PPC_SLBIA(IH) stringify_in_c(.long PPC_RAW_SLBIA(IH)) + hrmor = read_spr(SPR_HRMOR); asm volatile("sync; isync" ::: "memory"); write_spr(SPR_HRMOR, 0); - asm volatile("or 1,1,%0; slbia 7; sync; isync" :: "r"(hrmor) : "memory"); + asm volatile("or 1,1,%0;" PPC_SLBIA(7)"; sync; isync" :: "r"(hrmor) : "memory"); #endif main(); |