diff options
| author | Nico Huber <nico.h@gmx.de> | 2020-10-04 14:42:08 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-10-21 14:37:48 +0000 |
| commit | 9f7b36a540a89a594bcdeeda77be82801cb8b88d (patch) | |
| tree | a80015cde8c20e1298f49c35181ce8a1a8e60d42 | |
| parent | 947dc64d21e75af94bfddb36ad6b921d47a1e453 (diff) | |
mb/asus/f2a85-m_pro: Use `irq` in dt for single-byte registers
The `io` statement will prepare a 16-bit write, hence use `irq` for
miscellaneous 8-bit registers and fix actual `io` settings (i.e. merge
0x61 writes into 0x60). Note, using `irq` is still just a hack as these
are neither I/O nor IRQs, but it's common practice in coreboot.
Change-Id: I2e1c2286be726d126598cc4a97bb15a57faef42f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
| -rw-r--r-- | src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb | 124 |
1 files changed, 61 insertions, 63 deletions
diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb index c9de54c05c..c05857f6d0 100644 --- a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb +++ b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb @@ -45,83 +45,81 @@ chip northbridge/amd/agesa/family15tn/root_complex end device pnp 2e.6 off end # CIR device pnp 2e.7 on # GPIO6, GPIO7, GPIO8 - io 0xe0 = 0x7f - io 0xe1 = 0x10 - io 0xe2 = 0x00 - io 0xe3 = 0x00 - io 0xe4 = 0xff - io 0xe5 = 0xff - io 0xe6 = 0xff - io 0xe7 = 0xff - io 0xec = 0x00 - io 0xed = 0xff - io 0xf4 = 0xff - io 0xf5 = 0xff - io 0xf6 = 0x00 - io 0xf7 = 0x00 - io 0xf8 = 0x00 + irq 0xe0 = 0x7f + irq 0xe1 = 0x10 + irq 0xe2 = 0x00 + irq 0xe3 = 0x00 + irq 0xe4 = 0xff + irq 0xe5 = 0xff + irq 0xe6 = 0xff + irq 0xe7 = 0xff + irq 0xec = 0x00 + irq 0xed = 0xff + irq 0xf4 = 0xff + irq 0xf5 = 0xff + irq 0xf6 = 0x00 + irq 0xf7 = 0x00 + irq 0xf8 = 0x00 end device pnp 2e.8 on # WDT1, GPIO0, GPIO1 - io 0x30 = 0x00 - io 0x60 = 0x00 - io 0x61 = 0x00 - io 0xe0 = 0xff - io 0xe1 = 0xff - io 0xe2 = 0xff - io 0xe3 = 0xff - io 0xe4 = 0xff - io 0xf0 = 0xff - io 0xf1 = 0x28 - io 0xf2 = 0x00 - io 0xf3 = 0x00 - io 0xf4 = 0x08 - io 0xf5 = 0xff - io 0xf6 = 0x00 - io 0xf7 = 0xff + irq 0x30 = 0x00 + io 0x60 = 0x00 + irq 0xe0 = 0xff + irq 0xe1 = 0xff + irq 0xe2 = 0xff + irq 0xe3 = 0xff + irq 0xe4 = 0xff + irq 0xf0 = 0xff + irq 0xf1 = 0x28 + irq 0xf2 = 0x00 + irq 0xf3 = 0x00 + irq 0xf4 = 0x08 + irq 0xf5 = 0xff + irq 0xf6 = 0x00 + irq 0xf7 = 0xff end device pnp 2e.9 on # GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, GPIO8 - io 0x30 = 0xfe - io 0xe0 = 0xff - io 0xe1 = 0x90 - io 0xe2 = 0x00 - io 0xe3 = 0x00 - io 0xe4 = 0x7f - io 0xe5 = 0x76 - io 0xe6 = 0x00 - io 0xe7 = 0x00 - io 0xe8 = 0x00 - io 0xe9 = 0x00 - io 0xea = 0x00 - io 0xeb = 0x00 - io 0xee = 0x00 - io 0xf0 = 0xff - io 0xf1 = 0x7b - io 0xf2 = 0x00 - io 0xf4 = 0xff - io 0xf5 = 0xef - io 0xf6 = 0x00 - io 0xf7 = 0x00 - io 0xfe = 0x00 + irq 0x30 = 0xfe + irq 0xe0 = 0xff + irq 0xe1 = 0x90 + irq 0xe2 = 0x00 + irq 0xe3 = 0x00 + irq 0xe4 = 0x7f + irq 0xe5 = 0x76 + irq 0xe6 = 0x00 + irq 0xe7 = 0x00 + irq 0xe8 = 0x00 + irq 0xe9 = 0x00 + irq 0xea = 0x00 + irq 0xeb = 0x00 + irq 0xee = 0x00 + irq 0xf0 = 0xff + irq 0xf1 = 0x7b + irq 0xf2 = 0x00 + irq 0xf4 = 0xff + irq 0xf5 = 0xef + irq 0xf6 = 0x00 + irq 0xf7 = 0x00 + irq 0xfe = 0x00 end device pnp 2e.a on # ACPI - io 0xe6 = 0x4c - io 0xe7 = 0x11 - io 0xf2 = 0x5d + irq 0xe6 = 0x4c + irq 0xe7 = 0x11 + irq 0xf2 = 0x5d end device pnp 2e.b on # Hardware Monitor, Front Panel LED - io 0x30 = 0x01 - io 0x60 = 0x02 - io 0x61 = 0x90 - io 0xe2 = 0x7f - io 0xe4 = 0xf1 + irq 0x30 = 0x01 + io 0x60 = 0x0290 + irq 0xe2 = 0x7f + irq 0xe4 = 0xf1 end device pnp 2e.d off end # WDT1 device pnp 2e.e off end # CIR WAKE-UP device pnp 2e.f off # GPIO Push-pull/Open-drain selection - io 0xe6 = 7f + irq 0xe6 = 7f end device pnp 2e.14 off # PORT80 UART - io 0xe0 = 0x00 + irq 0xe0 = 0x00 end device pnp 2e.16 off end # Deep Sleep end |