asus/f2a85-m: switch away from ROMCC_BOOTBLOCK

Change-Id: I1d7127e2f9bd5bd9677feb2b0e686a854c4e3885
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37727
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

4 files changed, 70 insertions, 69 deletions

diff --git a/src/mainboard/asus/f2a85-m/Kconfig b/src/mainboard/asus/f2a85-m/Kconfig
index cd10e536a4..c1dd063c77 100644
--- a/src/mainboard/asus/f2a85-m/Kconfig
+++ b/src/mainboard/asus/f2a85-m/Kconfig
@@ -18,7 +18,6 @@ if BOARD_ASUS_F2A85_M || BOARD_ASUS_F2A85_M_PRO || BOARD_ASUS_F2A85_M_LE
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
-	select ROMCC_BOOTBLOCK
 	select CPU_AMD_AGESA_FAMILY15_TN
 	select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
 	select SOUTHBRIDGE_AMD_AGESA_HUDSON
diff --git a/src/mainboard/asus/f2a85-m/Makefile.inc b/src/mainboard/asus/f2a85-m/Makefile.inc
index f8895faa92..4dde2cfd1e 100644
--- a/src/mainboard/asus/f2a85-m/Makefile.inc
+++ b/src/mainboard/asus/f2a85-m/Makefile.inc
@@ -13,6 +13,8 @@
 # GNU General Public License for more details.
 #
 
+bootblock-y += bootblock.c
+
 romstage-y += buildOpts.c
 romstage-y += BiosCallOuts.c
 romstage-y += OemCustomize.c
diff --git a/src/mainboard/asus/f2a85-m/bootblock.c b/src/mainboard/asus/f2a85-m/bootblock.c
new file mode 100644
index 0000000000..648f55a559
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m/bootblock.c
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 Rudolf Marek <r.marek@assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootblock_common.h>
+#include <device/pnp_type.h>
+#include <southbridge/amd/common/amd_defs.h>
+#include <stdint.h>
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8728f/it8728f.h>
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct6779d/nct6779d.h>
+
+#define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x))
+
+static void sbxxx_enable_48mhzout(void)
+{
+	/* most likely programming to 48MHz out signal */
+	u32 reg32;
+	reg32 = SB_MMIO_MISC32(0x28);
+	reg32 &= 0xffc7ffff;
+	reg32 |= 0x00100000;
+	SB_MMIO_MISC32(0x28) = reg32;
+
+	reg32 = SB_MMIO_MISC32(0x40);
+	reg32 &= ~0x80u;
+	SB_MMIO_MISC32(0x40) = reg32;
+}
+
+static void superio_init_m(void)
+{
+	pnp_devfn_t uart = PNP_DEV(0x2e, IT8728F_SP1);
+	pnp_devfn_t gpio = PNP_DEV(0x2e, IT8728F_GPIO);
+
+	ite_kill_watchdog(gpio);
+	ite_enable_serial(uart, CONFIG_TTYS0_BASE);
+	ite_enable_3vsbsw(gpio);
+}
+
+static void superio_init_m_pro(void)
+{
+	pnp_devfn_t uart = PNP_DEV(0x2e, NCT6779D_SP1);
+
+	nuvoton_enable_serial(uart, CONFIG_TTYS0_BASE);
+}
+
+void bootblock_mainboard_early_init(void)
+{
+	/* enable SIO clock */
+	sbxxx_enable_48mhzout();
+
+	if (CONFIG(BOARD_ASUS_F2A85_M_PRO))
+		superio_init_m_pro();
+	else
+		superio_init_m();
+}
diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c
index 8a48e0080c..3aa29c8ce3 100644
--- a/src/mainboard/asus/f2a85-m/romstage.c
+++ b/src/mainboard/asus/f2a85-m/romstage.c
@@ -15,84 +15,16 @@
  */
 
 #include <arch/io.h>
-#include <console/console.h>
-#include <device/pnp_type.h>
-#include <device/pci_ops.h>
 #include <northbridge/amd/agesa/state_machine.h>
-#include <southbridge/amd/common/amd_defs.h>
-#include <southbridge/amd/agesa/hudson/hudson.h>
 #include <southbridge/amd/agesa/hudson/smbus.h>
 #include <stdint.h>
-#include <superio/ite/common/ite.h>
-#include <superio/ite/it8728f/it8728f.h>
-#include <superio/nuvoton/common/nuvoton.h>
-#include <superio/nuvoton/nct6779d/nct6779d.h>
-
-#define MMIO_NON_POSTED_START 0xfed00000
-#define MMIO_NON_POSTED_END   0xfedfffff
-#define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x))
-
-static void sbxxx_enable_48mhzout(void)
-{
-	/* most likely programming to 48MHz out signal */
-	u32 reg32;
-	reg32 = SB_MMIO_MISC32(0x28);
-	reg32 &= 0xffc7ffff;
-	reg32 |= 0x00100000;
-	SB_MMIO_MISC32(0x28) = reg32;
-
-	reg32 = SB_MMIO_MISC32(0x40);
-	reg32 &= ~0x80u;
-	SB_MMIO_MISC32(0x40) = reg32;
-}
-
-static void superio_init_m(void)
-{
-	pnp_devfn_t uart = PNP_DEV(0x2e, IT8728F_SP1);
-	pnp_devfn_t gpio = PNP_DEV(0x2e, IT8728F_GPIO);
-
-	ite_kill_watchdog(gpio);
-	ite_enable_serial(uart, CONFIG_TTYS0_BASE);
-	ite_enable_3vsbsw(gpio);
-}
-
-static void superio_init_m_pro(void)
-{
-	pnp_devfn_t uart = PNP_DEV(0x2e, NCT6779D_SP1);
-
-	nuvoton_enable_serial(uart, CONFIG_TTYS0_BASE);
-}
 
 void board_BeforeAgesa(struct sysinfo *cb)
 {
 	u8 byte;
-	pci_devfn_t dev;
-
-	/* enable SIO LPC decode */
-	dev = PCI_DEV(0, 0x14, 3);
-	byte = pci_read_config8(dev, 0x48);
-	byte |= 3;		/* 2e, 2f */
-	pci_write_config8(dev, 0x48, byte);
-
-	/* enable serial decode */
-	byte = pci_read_config8(dev, 0x44);
-	byte |= (1 << 6);  /* 0x3f8 */
-	pci_write_config8(dev, 0x44, byte);
 
 	post_code(0x30);
 
-	/* enable SB MMIO space */
-	outb(0x24, 0xcd6);
-	outb(0x1, 0xcd7);
-
-	/* enable SIO clock */
-	sbxxx_enable_48mhzout();
-
-	if (CONFIG(BOARD_ASUS_F2A85_M_PRO))
-		superio_init_m_pro();
-	else
-		superio_init_m();
-
 	/* turn on secondary smbus at b20 */
 	outb(0x28, 0xcd6);
 	byte = inb(0xcd7);