diff options
| author | Sean Rhodes <sean@starlabs.systems> | 2022-09-15 12:12:43 +0100 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2022-09-19 14:55:29 +0000 |
| commit | 9f44a8cc39542906d2571e02fe2696ae11ded958 (patch) | |
| tree | 85e5369ded1b858289f8928046f45f920654a1cd | |
| parent | 7ef5376123d4d0ebb811795fcee1de7066f65a0f (diff) | |
soc/intel/apollolake: Add bits of GEN_PMCON2 register
The values in this patch were found in the following datasheets:
* 334819 (APL)
* 336561 (GLK)
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ie7d40395d754b2abdf9079d6ee5e8ab8c536d449
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67661
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/pm.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index 1e6a927613..c1dee0c3cd 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -165,6 +165,11 @@ WARM_RESET_STS | GLOBAL_RESET_STS | \ SRS | MS4V) #define GEN_PMCON2 0x1024 +# define LPC_LPB_CLK_CTRL ((1 << 11) | (1 << 12) | (1 << 13)) +# define BIOS_PCI_EXP_EN (1 << 10) +# define PWRBTN_LVL (1 << 9) +# define SMI_LOCK (1 << 4) +# define PER_SMI_SEL (1 << 0) #define GEN_PMCON3 0x1028 # define SLP_S3_ASSERT_WIDTH_SHIFT 10 # define SLP_S3_ASSERT_MASK (0x3 << SLP_S3_ASSERT_WIDTH_SHIFT) |