diff options
| author | David Wu <david_wu@quanta.corp-partner.google.com> | 2021-11-10 15:20:06 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-11-25 10:41:12 +0000 |
| commit | 9ed2490e5bbc5f02e90f521f52b1f9da3b0cd0bb (patch) | |
| tree | 6397a1ce266a144b7059a603eddc34cb95c88021 | |
| parent | 281e2c1987f6d628fbbcb9bb78f632253b7cebe6 (diff) | |
mb/google/brya/var/kano: set power limits for thermal
Set power limits for kano based on CPU SKUs.
BUG=b:205648035
TEST=build pass
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I25cf9be68f8981d8307b4c15ab9f65b59058fb19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
| -rw-r--r-- | src/mainboard/google/brya/variants/kano/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/kano/ramstage.c | 18 |
2 files changed, 19 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/kano/Makefile.inc b/src/mainboard/google/brya/variants/kano/Makefile.inc index 9ea19ded56..66dcf7e1ac 100644 --- a/src/mainboard/google/brya/variants/kano/Makefile.inc +++ b/src/mainboard/google/brya/variants/kano/Makefile.inc @@ -6,3 +6,4 @@ romstage-y += gpio.c ramstage-y += gpio.c ramstage-$(CONFIG_FW_CONFIG) += variant.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/brya/variants/kano/ramstage.c b/src/mainboard/google/brya/variants/kano/ramstage.c new file mode 100644 index 0000000000..9b26cbb0f2 --- /dev/null +++ b/src/mainboard/google/brya/variants/kano/ramstage.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <device/pci_ids.h> + +const struct cpu_power_limits limits[] = { + /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ + { PCI_DEVICE_ID_INTEL_ADL_P_ID_7, 15, 12000, 15000, 40000, 40000, 105000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_6, 15, 12000, 15000, 40000, 40000, 105000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_5, 28, 18000, 28000, 40000, 40000, 105000 }, + { PCI_DEVICE_ID_INTEL_ADL_P_ID_3, 28, 18000, 28000, 40000, 40000, 105000 }, +}; + +void variant_devtree_update(void) +{ + size_t total_entries = ARRAY_SIZE(limits); + variant_update_power_limits(limits, total_entries); +} |