AGESA_LEGACY: Apply final cleanup and file removals

With no boards left using AGESA_LEGACY, wipe out remains
of that everywhere in the tree.

Change-Id: I0ddc1f400e56e42fe8a43b4766195e3a187dcea6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

32 files changed, 12 insertions, 918 deletions

diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig
index 602a9b0528..77db54cb58 100644
--- a/src/cpu/amd/agesa/Kconfig
+++ b/src/cpu/amd/agesa/Kconfig
@@ -30,21 +30,10 @@ config CPU_AMD_AGESA
 	select UDELAY_LAPIC
 	select LAPIC_MONOTONIC_TIMER
 	select SPI_FLASH if HAVE_ACPI_RESUME
-	select POSTCAR_STAGE if !AGESA_LEGACY_WRAPPER
+	select POSTCAR_STAGE
 
 if CPU_AMD_AGESA
 
-config AGESA_LEGACY
-	def_bool n
-
-config AGESA_LEGACY_WRAPPER
-	bool
-	default AGESA_LEGACY
-
-config AGESA_NO_LEGACY
-	bool
-	default !AGESA_LEGACY
-
 config XIP_ROM_SIZE
 	hex
 	default 0x100000
diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc
index 470e62f25d..e581661c06 100644
--- a/src/cpu/amd/agesa/Makefile.inc
+++ b/src/cpu/amd/agesa/Makefile.inc
@@ -18,12 +18,6 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15) += family15
 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += family15tn
 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb
 
-ifeq ($(CONFIG_AGESA_LEGACY), y)
-cpu_incs-y += $(src)/cpu/amd/agesa/cache_as_ram_legacy.inc
-endif
-
-ramstage-$(CONFIG_AGESA_LEGACY_WRAPPER) += amd_late_init.c
-
 ifeq ($(CONFIG_HAVE_ACPI_RESUME), y)
 
 $(obj)/coreboot_s3nv.rom: $(obj)/config.h
diff --git a/src/cpu/amd/agesa/amd_late_init.c b/src/cpu/amd/agesa/amd_late_init.c
deleted file mode 100644
index 9bb6b2784e..0000000000
--- a/src/cpu/amd/agesa/amd_late_init.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/acpi.h>
-#include <bootstate.h>
-
-#include <northbridge/amd/agesa/agesawrapper.h>
-
-#if IS_ENABLED(CONFIG_AMD_SB_CIMX)
-#include <sb_cimx.h>
-#endif
-
-static void agesawrapper_post_device(void *unused)
-{
-	if (acpi_is_wakeup_s3())
-		return;
-
-	agesawrapper_amdinitlate();
-
-#if IS_ENABLED(CONFIG_AMD_SB_CIMX)
-	sb_Late_Post();
-#endif
-	if (!acpi_s3_resume_allowed())
-		return;
-
-	agesawrapper_amdS3Save();
-}
-
-BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT,
-			agesawrapper_post_device, NULL);
diff --git a/src/cpu/amd/agesa/cache_as_ram_legacy.inc b/src/cpu/amd/agesa/cache_as_ram_legacy.inc
deleted file mode 100644
index 55480070c9..0000000000
--- a/src/cpu/amd/agesa/cache_as_ram_legacy.inc
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/******************************************************************************
- * AMD Generic Encapsulated Software Architecture
- *
- * $Workfile:: cache_as_ram.inc
- *
- * Description: cache_as_ram.inc - AGESA Module Entry Point for GCC complier
- *
- ******************************************************************************
- */
-
-#include "gcccar.inc"
-#include <cpu/x86/cache.h>
-
-/*
- * XMM map:
- *   xmm0: BIST
- *   xmm1: backup ebx -- cpu_init_detected
- */
-
-.code32
-.globl cache_as_ram_setup, disable_cache_as_ram, cache_as_ram_setup_out
-
-cache_as_ram_setup:
-
-  post_code(0xa0)
-
-  /* enable SSE2 128bit instructions */
-  /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */
-
-  movl %cr4, %eax
-  orl $(3 << 9), %eax
-  movl %eax, %cr4
-
-  /* Get the cpu_init_detected */
-  mov $1, %eax
-  cpuid
-  shr $24, %ebx
-
-  /* Save the BIST result */
-  cvtsi2sd  %ebp, %xmm0
-
-  /* for normal part %ebx already contain cpu_init_detected from fallback call */
-
-  /* Save the cpu_init_detected */
-  cvtsi2sd  %ebx, %xmm1
-
-  post_code(0xa1)
-
-  AMD_ENABLE_STACK
-
-  /* Align the stack. */
-  and     $0xFFFFFFF0, %esp
-
-#ifdef __x86_64__
-  /* switch to 64 bit long mode */
-  mov     %esi, %ecx
-  add     $0, %ecx # core number
-  xor     %eax, %eax
-  lea     (0x1000+0x23)(%ecx), %edi
-  mov     %edi, (%ecx)
-  mov     %eax, 4(%ecx)
-
-  lea     0x1000(%ecx), %edi
-  movl    $0x000000e3, 0x00(%edi)
-  movl    %eax, 0x04(%edi)
-  movl    $0x400000e3, 0x08(%edi)
-  movl    %eax, 0x0c(%edi)
-  movl    $0x800000e3, 0x10(%edi)
-  movl    %eax, 0x14(%edi)
-  movl    $0xc00000e3, 0x18(%edi)
-  movl    %eax, 0x1c(%edi)
-
-  # load ROM based identity mapped page tables
-  mov     %ecx, %eax
-  mov     %eax, %cr3
-
-  # enable PAE
-  mov     %cr4, %eax
-  bts     $5, %eax
-  mov     %eax, %cr4
-
-  # enable long mode
-  mov     $0xC0000080, %ecx
-  rdmsr
-  bts     $8, %eax
-  wrmsr
-
-  # enable paging
-  mov     %cr0, %eax
-  bts     $31, %eax
-  mov     %eax, %cr0
-
-  # use call far to switch to 64-bit code segment
-  ljmp $0x18, $1f
-1:
-  /* Pass the cpu_init_detected */
-  cvtsd2si        %xmm1, %esi
-
-  /* Pass the BIST result */
-  cvtsd2si        %xmm0, %edi
-
-
-  .code64
-  call    cache_as_ram_main
-  .code32
-
-#else
-
-  /* Restore the BIST result */
-  cvtsd2si  %xmm0, %edx
-
-  /* Restore the  cpu_init_detected */
-  cvtsd2si  %xmm1, %ebx
-
-  /* Must maintain 16-byte stack alignment here. */
-  pushl $0x0
-  pushl $0x0
-  pushl %ebx  /* init detected */
-  pushl %edx  /* bist */
-  call  cache_as_ram_main
-#endif
-
-  /* Should never see this postcode */
-  post_code(0xaf)
-stop:
-  jmp stop
-
-disable_cache_as_ram:
-  /* Save return stack */
-  movd 0(%esp), %xmm1
-  movd %esp, %xmm0
-
-  /* Disable cache */
-  movl	%cr0, %eax
-  orl	$CR0_CacheDisable, %eax
-  movl	%eax, %cr0
-
-  AMD_DISABLE_STACK
-
-  /* enable cache */
-  movl %cr0, %eax
-  andl $0x9fffffff, %eax
-  movl %eax, %cr0
-  xorl %eax, %eax
-
-  /* Restore the return stack */
-  wbinvd
-  movd %xmm0, %esp
-  movd %xmm1, (%esp)
-  ret
-
-cache_as_ram_setup_out:
-#ifdef __x86_64__
-.code64
-#endif
diff --git a/src/cpu/amd/agesa/family12/Makefile.inc b/src/cpu/amd/agesa/family12/Makefile.inc
index 5673c6b502..1a7465d81f 100644
--- a/src/cpu/amd/agesa/family12/Makefile.inc
+++ b/src/cpu/amd/agesa/family12/Makefile.inc
@@ -28,7 +28,7 @@
 #*****************************************************************************
 
 romstage-y += fixme.c
-romstage-$(CONFIG_AGESA_NO_LEGACY) += romstage.c
+romstage-y += romstage.c
 
 ramstage-y += fixme.c
 ramstage-y += chip_name.c
diff --git a/src/cpu/amd/agesa/family12/romstage.c b/src/cpu/amd/agesa/family12/romstage.c
index 2a183270d7..9d617efe4b 100644
--- a/src/cpu/amd/agesa/family12/romstage.c
+++ b/src/cpu/amd/agesa/family12/romstage.c
@@ -14,12 +14,7 @@
  * GNU General Public License for more details.
  */
 
-#include <console/console.h>
-#include <cpu/amd/car.h>
-
-#include <northbridge/amd/agesa/agesawrapper.h>
 #include <northbridge/amd/agesa/state_machine.h>
-#include <northbridge/amd/agesa/agesa_helper.h>
 
 #include "sb_cimx.h"
 #include "SbPlatform.h"
@@ -33,30 +28,3 @@ void platform_once(struct sysinfo *cb)
 
 	board_BeforeAgesa(cb);
 }
-
-void agesa_main(struct sysinfo *cb)
-{
-	post_code(0x36);
-	agesawrapper_amdinitreset();
-
-	post_code(0x37);
-	agesawrapper_amdinitearly();
-
-	printk(BIOS_INFO, "Normal boot\n");
-
-	post_code(0x38);
-	agesawrapper_amdinitpost();
-}
-
-void agesa_postcar(struct sysinfo *cb)
-{
-	printk(BIOS_INFO, "Normal boot postcar\n");
-
-	post_code(0x39);
-	printk(BIOS_DEBUG, "sb_before_pci_init ");
-	sb_before_pci_init();
-	printk(BIOS_DEBUG, "passed.\n");
-
-	post_code(0x40);
-	agesawrapper_amdinitenv();
-}
diff --git a/src/cpu/amd/agesa/family14/Makefile.inc b/src/cpu/amd/agesa/family14/Makefile.inc
index 71d15fbbf6..3da8dd599b 100644
--- a/src/cpu/amd/agesa/family14/Makefile.inc
+++ b/src/cpu/amd/agesa/family14/Makefile.inc
@@ -14,7 +14,7 @@
 #
 
 romstage-y += fixme.c
-romstage-$(CONFIG_AGESA_NO_LEGACY) += romstage.c
+romstage-y += romstage.c
 
 ramstage-y += fixme.c
 ramstage-y += chip_name.c
diff --git a/src/cpu/amd/agesa/family14/romstage.c b/src/cpu/amd/agesa/family14/romstage.c
index 53e6a1c623..7fd522fb1e 100644
--- a/src/cpu/amd/agesa/family14/romstage.c
+++ b/src/cpu/amd/agesa/family14/romstage.c
@@ -14,12 +14,8 @@
  * GNU General Public License for more details.
  */
 
-#include <console/console.h>
-#include <cpu/amd/car.h>
 
-#include <northbridge/amd/agesa/agesawrapper.h>
 #include <northbridge/amd/agesa/state_machine.h>
-#include <northbridge/amd/agesa/agesa_helper.h>
 
 #include <sb_cimx.h>
 
@@ -29,44 +25,3 @@ void platform_once(struct sysinfo *cb)
 
 	board_BeforeAgesa(cb);
 }
-
-void agesa_main(struct sysinfo *cb)
-{
-	post_code(0x37);
-	agesawrapper_amdinitreset();
-
-	post_code(0x39);
-	agesawrapper_amdinitearly();
-
-	if (!cb->s3resume) {
-		printk(BIOS_INFO, "Normal boot\n");
-
-		post_code(0x40);
-		agesawrapper_amdinitpost();
-	} else {
-		printk(BIOS_INFO, "S3 detected\n");
-
-		post_code(0x60);
-		agesawrapper_amdinitresume();
-	}
-}
-
-void agesa_postcar(struct sysinfo *cb)
-{
-	if (!cb->s3resume) {
-		printk(BIOS_INFO, "Normal boot postcar\n");
-
-		post_code(0x41);
-		agesawrapper_amdinitenv();
-
-		post_code(0x42);
-		amd_initenv();
-	} else {
-		printk(BIOS_INFO, "S3 resume postcar\n");
-
-		post_code(0x61);
-		agesawrapper_amds3laterestore();
-
-		post_code(0x62);
-	}
-}
diff --git a/src/cpu/amd/agesa/family15/Makefile.inc b/src/cpu/amd/agesa/family15/Makefile.inc
index d7cdff7a30..d01cb2aec5 100644
--- a/src/cpu/amd/agesa/family15/Makefile.inc
+++ b/src/cpu/amd/agesa/family15/Makefile.inc
@@ -22,7 +22,7 @@ subdirs-y += ../../../x86/pae
 subdirs-y += ../../../x86/smm
 
 romstage-y += fixme.c
-romstage-$(CONFIG_AGESA_NO_LEGACY) += romstage.c
+romstage-y += romstage.c
 
 ramstage-y += fixme.c
 ramstage-y += chip_name.c
diff --git a/src/cpu/amd/agesa/family15/romstage.c b/src/cpu/amd/agesa/family15/romstage.c
index 7e65f81e1d..46c03910f7 100644
--- a/src/cpu/amd/agesa/family15/romstage.c
+++ b/src/cpu/amd/agesa/family15/romstage.c
@@ -20,8 +20,6 @@
 #include <console/console.h>
 #include <cpu/amd/car.h>
 
-#include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/agesa_helper.h>
 #include <northbridge/amd/agesa/state_machine.h>
 
 #include "northbridge/amd/agesa/family15/reset_test.h"
@@ -43,15 +41,8 @@ void platform_once(struct sysinfo *cb)
 	board_BeforeAgesa(cb);
 }
 
-void agesa_main(struct sysinfo *cb)
-{
-	post_code(0x37);
-	agesawrapper_amdinitreset();
-
-	post_code(0x3B);
-	agesawrapper_amdinitearly();
-
-	post_code(0x3C);
+#if 0
+	/* Was between EARLY and POST */
 
 	nb_Ht_Init();
 	post_code(0x3D);
@@ -63,16 +54,4 @@ void agesa_main(struct sysinfo *cb)
 		die("After soft_reset - shouldn't see this message!!!\n");
 	}
 
-	post_code(0x40);
-	agesawrapper_amdinitpost();
-
-	printk(BIOS_INFO, "Normal boot\n");
-}
-
-void agesa_postcar(struct sysinfo *cb)
-{
-	printk(BIOS_INFO, "Normal boot postcar\n");
-
-	post_code(0x41);
-	agesawrapper_amdinitenv();
-}
+#endif
diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc
index 4fcaff7405..98a7050c21 100644
--- a/src/cpu/amd/agesa/family15tn/Makefile.inc
+++ b/src/cpu/amd/agesa/family15tn/Makefile.inc
@@ -14,7 +14,6 @@
 #
 
 romstage-y += fixme.c
-romstage-$(CONFIG_AGESA_NO_LEGACY) += romstage.c
 
 ramstage-y += fixme.c
 ramstage-y += chip_name.c
diff --git a/src/cpu/amd/agesa/family15tn/romstage.c b/src/cpu/amd/agesa/family15tn/romstage.c
deleted file mode 100644
index fcf2f17fe5..0000000000
--- a/src/cpu/amd/agesa/family15tn/romstage.c
+++ /dev/null
@@ -1,62 +0,0 @@
-
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * Copyright (C) 2017 Kyösti Mälkki
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <cpu/amd/car.h>
-
-#include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/state_machine.h>
-#include <northbridge/amd/agesa/agesa_helper.h>
-
-void agesa_main(struct sysinfo *cb)
-{
-	post_code(0x37);
-	agesawrapper_amdinitreset();
-
-	post_code(0x39);
-	agesawrapper_amdinitearly();
-
-	if (!cb->s3resume) {
-		printk(BIOS_INFO, "Normal boot\n");
-
-		post_code(0x40);
-		agesawrapper_amdinitpost();
-	} else {
-		printk(BIOS_INFO, "S3 detected\n");
-
-		post_code(0x60);
-		agesawrapper_amdinitresume();
-	}
-}
-
-void agesa_postcar(struct sysinfo *cb)
-{
-	if (!cb->s3resume) {
-		printk(BIOS_INFO, "Normal boot postcar\n");
-
-		post_code(0x41);
-		agesawrapper_amdinitenv();
-	} else {
-		printk(BIOS_INFO, "S3 resume postcar\n");
-
-		post_code(0x61);
-		amd_initcpuio();
-
-		post_code(0x62);
-		agesawrapper_amds3laterestore();
-	}
-}
diff --git a/src/cpu/amd/agesa/family16kb/Makefile.inc b/src/cpu/amd/agesa/family16kb/Makefile.inc
index 31c3ecfabc..9367b458a3 100644
--- a/src/cpu/amd/agesa/family16kb/Makefile.inc
+++ b/src/cpu/amd/agesa/family16kb/Makefile.inc
@@ -14,7 +14,6 @@
 #
 
 romstage-y += fixme.c
-romstage-$(CONFIG_AGESA_NO_LEGACY) += romstage.c
 
 ramstage-y += fixme.c
 ramstage-y += chip_name.c
diff --git a/src/cpu/amd/agesa/family16kb/romstage.c b/src/cpu/amd/agesa/family16kb/romstage.c
deleted file mode 100644
index 3f9afce080..0000000000
--- a/src/cpu/amd/agesa/family16kb/romstage.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * Copyright (C) 2017 Kyösti Mälkki
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <cpu/amd/car.h>
-
-#include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/state_machine.h>
-#include <northbridge/amd/agesa/agesa_helper.h>
-
-void agesa_main(struct sysinfo *cb)
-{
-	post_code(0x37);
-	agesawrapper_amdinitreset();
-
-	post_code(0x39);
-	agesawrapper_amdinitearly();
-
-	if (!cb->s3resume) {
-		printk(BIOS_INFO, "Normal boot\n");
-
-		post_code(0x40);
-		agesawrapper_amdinitpost();
-
-	} else {
-		printk(BIOS_INFO, "S3 detected\n");
-
-		post_code(0x60);
-		agesawrapper_amdinitresume();
-	}
-}
-
-void agesa_postcar(struct sysinfo *cb)
-{
-	if (!cb->s3resume) {
-		printk(BIOS_INFO, "Normal boot postcar\n");
-
-		post_code(0x41);
-		agesawrapper_amdinitenv();
-	} else {
-		printk(BIOS_INFO, "S3 resume postcar\n");
-
-		post_code(0x61);
-		amd_initcpuio();
-
-		post_code(0x62);
-		agesawrapper_amds3laterestore();
-
-		post_code(0x63);
-	}
-}
diff --git a/src/drivers/amd/agesa/Makefile.inc b/src/drivers/amd/agesa/Makefile.inc
index 4d3dbf5cb9..4d5bd3e368 100644
--- a/src/drivers/amd/agesa/Makefile.inc
+++ b/src/drivers/amd/agesa/Makefile.inc
@@ -13,7 +13,7 @@
 
 ifeq ($(CONFIG_DRIVERS_AMD_PI),y)
 
-ifneq ($(CONFIG_AGESA_LEGACY_WRAPPER)$(CONFIG_BINARYPI_LEGACY_WRAPPER),y)
+ifneq ($(CONFIG_BINARYPI_LEGACY_WRAPPER),y)
 
 romstage-y += romstage.c
 romstage-y += mtrr_fixme.c
diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig
index ddb1151908..b7408d2595 100644
--- a/src/northbridge/amd/agesa/Kconfig
+++ b/src/northbridge/amd/agesa/Kconfig
@@ -18,7 +18,6 @@ config NORTHBRIDGE_AMD_AGESA
 	default CPU_AMD_AGESA
 	select RELOCATABLE_RAMSTAGE if EARLY_CBMEM_INIT
 	select CBMEM_TOP_BACKUP
-	select LATE_CBMEM_INIT if AGESA_LEGACY_WRAPPER
 
 if NORTHBRIDGE_AMD_AGESA
 
diff --git a/src/northbridge/amd/agesa/Makefile.inc b/src/northbridge/amd/agesa/Makefile.inc
index 7de920e616..b6ac7a4354 100644
--- a/src/northbridge/amd/agesa/Makefile.inc
+++ b/src/northbridge/amd/agesa/Makefile.inc
@@ -21,9 +21,4 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15) += family15
 subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN) += family15tn
 subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB) += family16kb
 
-ifeq ($(CONFIG_AGESA_LEGACY_WRAPPER), y)
-romstage-y += agesawrapper.c
-ramstage-y += agesawrapper.c
-endif
-
 endif
diff --git a/src/northbridge/amd/agesa/agesawrapper.c b/src/northbridge/amd/agesa/agesawrapper.c
deleted file mode 100644
index 768f10042f..0000000000
--- a/src/northbridge/amd/agesa/agesawrapper.c
+++ /dev/null
@@ -1,304 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011-2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <cbmem.h>
-#include <stdint.h>
-#include <string.h>
-
-#include <northbridge/amd/agesa/state_machine.h>
-#include <northbridge/amd/agesa/agesa_helper.h>
-#include <northbridge/amd/agesa/agesawrapper.h>
-#include <northbridge/amd/agesa/BiosCallOuts.h>
-#include "amdlib.h"
-
-#include "heapManager.h"
-
-static const struct OEM_HOOK *OemHook = &OemCustomize;
-
-#if defined(__PRE_RAM__)
-
-AGESA_STATUS agesawrapper_amdinitreset(void)
-{
-	AGESA_STATUS status;
-	AMD_INTERFACE_PARAMS AmdParamStruct;
-	AMD_RESET_PARAMS AmdResetParams;
-
-	memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
-	memset(&AmdResetParams, 0, sizeof(AMD_RESET_PARAMS));
-
-	AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET;
-	AmdParamStruct.AllocationMethod = ByHost;
-	AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS);
-	AmdParamStruct.NewStructPtr = &AmdResetParams;
-	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
-	AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout;
-	AmdParamStruct.StdHeader.Func = 0;
-	AmdParamStruct.StdHeader.ImageBasePtr = 0;
-
-	AmdCreateStruct(&AmdParamStruct);
-	AmdResetParams.HtConfig.Depth = 0;
-
-	status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr);
-	AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
-	AmdReleaseStruct(&AmdParamStruct);
-	return status;
-}
-
-AGESA_STATUS agesawrapper_amdinitearly(void)
-{
-	AGESA_STATUS status;
-	AMD_INTERFACE_PARAMS AmdParamStruct;
-	AMD_EARLY_PARAMS *AmdEarlyParamsPtr;
-
-	memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
-
-	AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY;
-	AmdParamStruct.AllocationMethod = PreMemHeap;
-	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
-	AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout;
-	AmdParamStruct.StdHeader.Func = 0;
-	AmdParamStruct.StdHeader.ImageBasePtr = 0;
-	AmdCreateStruct(&AmdParamStruct);
-
-	/* OEM Should Customize the defaults through this hook. */
-	AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr;
-	if (OemHook->InitEarly)
-		OemHook->InitEarly(AmdEarlyParamsPtr);
-
-	status = AmdInitEarly(AmdEarlyParamsPtr);
-	AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
-
-	AmdReleaseStruct(&AmdParamStruct);
-
-	return status;
-}
-
-AGESA_STATUS agesawrapper_amdinitpost(void)
-{
-	AGESA_STATUS status;
-	AMD_INTERFACE_PARAMS AmdParamStruct;
-	AMD_POST_PARAMS *PostParams;
-
-	memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
-
-	AmdParamStruct.AgesaFunctionName = AMD_INIT_POST;
-	AmdParamStruct.AllocationMethod = PreMemHeap;
-	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
-	AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout;
-	AmdParamStruct.StdHeader.Func = 0;
-	AmdParamStruct.StdHeader.ImageBasePtr = 0;
-
-	AmdCreateStruct(&AmdParamStruct);
-
-	/* OEM Should Customize the defaults through this hook. */
-	PostParams = (AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr;
-	if (OemHook->InitPost)
-		OemHook->InitPost(PostParams);
-
-	status = AmdInitPost(PostParams);
-	AGESA_EVENTLOG(status, &PostParams->StdHeader);
-
-	backup_top_of_low_cacheable(PostParams->MemConfig.Sub4GCacheTop);
-
-	AmdReleaseStruct(&AmdParamStruct);
-
-	return status;
-}
-
-AGESA_STATUS agesawrapper_amdinitresume(void)
-{
-	AGESA_STATUS status;
-	AMD_INTERFACE_PARAMS AmdParamStruct;
-	AMD_RESUME_PARAMS *AmdResumeParamsPtr;
-
-	memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
-
-	AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME;
-	AmdParamStruct.AllocationMethod = PreMemHeap;
-	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
-	AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout;
-	AmdParamStruct.StdHeader.Func = 0;
-	AmdParamStruct.StdHeader.ImageBasePtr = 0;
-	AmdCreateStruct(&AmdParamStruct);
-
-	AmdResumeParamsPtr = (AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr;
-
-	AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0;
-	AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0;
-	OemInitResume(&AmdResumeParamsPtr->S3DataBlock);
-
-	status = AmdInitResume(AmdResumeParamsPtr);
-
-	AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader);
-	AmdReleaseStruct(&AmdParamStruct);
-
-	return status;
-}
-
-AGESA_STATUS agesawrapper_amdinitenv(void)
-{
-	AGESA_STATUS status;
-	AMD_INTERFACE_PARAMS AmdParamStruct;
-	AMD_ENV_PARAMS *EnvParam;
-
-	/* Initialize heap space */
-	EmptyHeap();
-
-	memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
-
-	AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV;
-	AmdParamStruct.AllocationMethod = PostMemDram;
-	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
-	AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout;
-	AmdParamStruct.StdHeader.Func = 0;
-	AmdParamStruct.StdHeader.ImageBasePtr = 0;
-	AmdCreateStruct(&AmdParamStruct);
-	EnvParam = (AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr;
-
-	status = AmdInitEnv(EnvParam);
-	AGESA_EVENTLOG(status, &EnvParam->StdHeader);
-
-	AmdReleaseStruct(&AmdParamStruct);
-	return status;
-}
-
-AGESA_STATUS agesawrapper_amds3laterestore(void)
-{
-	AGESA_STATUS status;
-	AMD_INTERFACE_PARAMS AmdInterfaceParams;
-	AMD_S3LATE_PARAMS AmdS3LateParams;
-	AMD_S3LATE_PARAMS *AmdS3LateParamsPtr;
-
-	memset(&AmdS3LateParams, 0, sizeof(AMD_S3LATE_PARAMS));
-
-	AmdInterfaceParams.StdHeader.ImageBasePtr = 0;
-	AmdInterfaceParams.AllocationMethod = ByHost;
-	AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE;
-	AmdInterfaceParams.NewStructPtr = &AmdS3LateParams;
-	AmdInterfaceParams.StdHeader.CalloutPtr = &GetBiosCallout;
-	AmdS3LateParamsPtr = &AmdS3LateParams;
-	AmdInterfaceParams.NewStructSize = sizeof(AMD_S3LATE_PARAMS);
-
-	AmdCreateStruct(&AmdInterfaceParams);
-
-#if 0
-	/* TODO: What to do with NvStorage here? */
-	AmdS3LateParamsPtr->S3DataBlock.NvStorageSize = 0;
-#endif
-	AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0;
-	OemS3LateRestore(&AmdS3LateParamsPtr->S3DataBlock);
-
-	status = AmdS3LateRestore(AmdS3LateParamsPtr);
-	AGESA_EVENTLOG(status, &AmdInterfaceParams.StdHeader);
-	ASSERT(status == AGESA_SUCCESS);
-
-	return status;
-}
-
-#else /* __PRE_RAM__ */
-
-AGESA_STATUS agesawrapper_amdinitmid(void)
-{
-	AGESA_STATUS status;
-	AMD_INTERFACE_PARAMS AmdParamStruct;
-	AMD_MID_PARAMS *MidParam;
-
-	memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
-
-	AmdParamStruct.AgesaFunctionName = AMD_INIT_MID;
-	AmdParamStruct.AllocationMethod = PostMemDram;
-	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
-	AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout;
-	AmdParamStruct.StdHeader.Func = 0;
-	AmdParamStruct.StdHeader.ImageBasePtr = 0;
-
-	AmdCreateStruct(&AmdParamStruct);
-
-	/* OEM Should Customize the defaults through this hook. */
-	MidParam = (AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr;
-	if (OemHook->InitMid)
-		OemHook->InitMid(MidParam);
-
-	status = AmdInitMid(MidParam);
-	AGESA_EVENTLOG(status, &MidParam->StdHeader);
-	AmdReleaseStruct(&AmdParamStruct);
-
-	return status;
-}
-
-AGESA_STATUS agesawrapper_amdS3Save(void)
-{
-	AGESA_STATUS status;
-	AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr;
-	AMD_INTERFACE_PARAMS AmdInterfaceParams;
-
-	memset(&AmdInterfaceParams, 0, sizeof(AMD_INTERFACE_PARAMS));
-
-	AmdInterfaceParams.StdHeader.ImageBasePtr = 0;
-	AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
-	AmdInterfaceParams.StdHeader.CalloutPtr = &GetBiosCallout;
-	AmdInterfaceParams.AllocationMethod = PostMemDram;
-	AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE;
-	AmdInterfaceParams.StdHeader.AltImageBasePtr = 0;
-	AmdInterfaceParams.StdHeader.Func = 0;
-	AmdCreateStruct(&AmdInterfaceParams);
-
-	AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *) AmdInterfaceParams.NewStructPtr;
-	AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader;
-
-	status = AmdS3Save(AmdS3SaveParamsPtr);
-	AGESA_EVENTLOG(status, &AmdInterfaceParams.StdHeader);
-	ASSERT(status == AGESA_SUCCESS);
-
-	OemS3Save(&AmdS3SaveParamsPtr->S3DataBlock);
-
-	AmdReleaseStruct(&AmdInterfaceParams);
-
-	return status;
-}
-
-AGESA_STATUS agesawrapper_amdinitlate(void)
-{
-	AGESA_STATUS status;
-	AMD_INTERFACE_PARAMS AmdParamStruct;
-	AMD_LATE_PARAMS *AmdLateParams;
-
-	memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS));
-
-	AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE;
-	AmdParamStruct.AllocationMethod = PostMemDram;
-	AmdParamStruct.StdHeader.AltImageBasePtr = 0;
-	AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout;
-	AmdParamStruct.StdHeader.Func = 0;
-	AmdParamStruct.StdHeader.ImageBasePtr = 0;
-
-#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) || \
-	IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY16_KB)
-	AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM;
-#endif
-
-	AmdCreateStruct(&AmdParamStruct);
-	AmdLateParams = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr;
-	status = AmdInitLate(AmdLateParams);
-	AGESA_EVENTLOG(status, &AmdLateParams->StdHeader);
-	ASSERT(status == AGESA_SUCCESS);
-
-	agesawrapper_setlateinitptr(AmdLateParams);
-
-	/* No AmdReleaseStruct(&AmdParamStruct), we need AmdLateParams later. */
-	return status;
-}
-
-#endif /* __PRE_RAM__ */
diff --git a/src/northbridge/amd/agesa/agesawrapper.h b/src/northbridge/amd/agesa/agesawrapper.h
index 9ba0baa568..d7a137c679 100644
--- a/src/northbridge/amd/agesa/agesawrapper.h
+++ b/src/northbridge/amd/agesa/agesawrapper.h
@@ -16,8 +16,7 @@
 #ifndef _AGESAWRAPPER_H_
 #define _AGESAWRAPPER_H_
 
-#if IS_ENABLED(CONFIG_AGESA_LEGACY_WRAPPER) || \
-	IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)
+#if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)
 
 #include <stdint.h>
 #include "Porting.h"
@@ -52,20 +51,6 @@ static inline int agesawrapper_amds3laterestore(void) { return -1; }
 
 #endif
 
-#if IS_ENABLED(CONFIG_AGESA_LEGACY_WRAPPER)
-struct OEM_HOOK
-{
-	/* romstage */
-	AGESA_STATUS (*InitEarly)(AMD_EARLY_PARAMS *);
-	AGESA_STATUS (*InitPost)(AMD_POST_PARAMS *);
-
-	/* ramstage */
-	AGESA_STATUS (*InitMid)(AMD_MID_PARAMS *);
-};
-
-extern const struct OEM_HOOK OemCustomize;
-#endif
-
 #if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)
 const void *agesawrapper_locate_module (const CHAR8 name[8]);
 
diff --git a/src/northbridge/amd/agesa/family12/Makefile.inc b/src/northbridge/amd/agesa/family12/Makefile.inc
index 41c40c3915..ad39325247 100644
--- a/src/northbridge/amd/agesa/family12/Makefile.inc
+++ b/src/northbridge/amd/agesa/family12/Makefile.inc
@@ -17,7 +17,5 @@ romstage-y += dimmSpd.c
 
 ramstage-y += northbridge.c
 
-ifneq ($(CONFIG_AGESA_LEGACY_WRAPPER), y)
 romstage-y += state_machine.c
 ramstage-y += state_machine.c
-endif
diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c
index 4995e648a0..d77dbbb86d 100644
--- a/src/northbridge/amd/agesa/family12/northbridge.c
+++ b/src/northbridge/amd/agesa/family12/northbridge.c
@@ -33,7 +33,6 @@
 
 #include "sb_cimx.h"
 
-#include <northbridge/amd/agesa/agesawrapper.h>
 #include <northbridge/amd/agesa/state_machine.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
 
@@ -597,26 +596,6 @@ static void domain_set_resources(device_t dev)
 }
 
 
-static void domain_enable_resources(device_t dev)
-{
-#if IS_ENABLED(CONFIG_AGESA_LEGACY_WRAPPER)
-	printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__);
-
-	/* Must be called after PCI enumeration and resource allocation */
-#if IS_ENABLED(CONFIG_AMD_SB_CIMX)
-	sb_After_Pci_Init();
-	sb_Mid_Post_Init();
-#endif
-
-	/* Enable MMIO on AMD CPU Address Map Controller */
-	amd_initcpuio();
-
-	agesawrapper_amdinitmid();
-	printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__);
-#endif
-}
-
-
 /* Bus related code */
 
 static void cpu_bus_init(device_t dev)
@@ -757,7 +736,6 @@ struct chip_operations northbridge_amd_agesa_family12_ops = {
 static struct device_operations pci_domain_ops = {
 	.read_resources   = domain_read_resources,
 	.set_resources    = domain_set_resources,
-	.enable_resources = domain_enable_resources,
 	.init             = DEVICE_NOOP,
 	.scan_bus         = pci_domain_scan_bus,
 };
diff --git a/src/northbridge/amd/agesa/family14/Makefile.inc b/src/northbridge/amd/agesa/family14/Makefile.inc
index 41c40c3915..ad39325247 100644
--- a/src/northbridge/amd/agesa/family14/Makefile.inc
+++ b/src/northbridge/amd/agesa/family14/Makefile.inc
@@ -17,7 +17,5 @@ romstage-y += dimmSpd.c
 
 ramstage-y += northbridge.c
 
-ifneq ($(CONFIG_AGESA_LEGACY_WRAPPER), y)
 romstage-y += state_machine.c
 ramstage-y += state_machine.c
-endif
diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c
index d0abcfd97b..ab444bd7bf 100644
--- a/src/northbridge/amd/agesa/family14/northbridge.c
+++ b/src/northbridge/amd/agesa/family14/northbridge.c
@@ -31,7 +31,6 @@
 #include <cpu/x86/lapic.h>
 #include <cpu/amd/mtrr.h>
 
-#include <northbridge/amd/agesa/agesawrapper.h>
 #include <northbridge/amd/agesa/state_machine.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
 
@@ -580,32 +579,6 @@ static void domain_set_resources(device_t dev)
 	printk(BIOS_DEBUG, "  adsr - leaving this lovely routine.\n");
 }
 
-static void domain_enable_resources(device_t dev)
-{
-#if IS_ENABLED(CONFIG_AGESA_LEGACY_WRAPPER)
-	/* Must be called after PCI enumeration and resource allocation */
-	printk(BIOS_DEBUG, "\nFam14h - %s\n", __func__);
-
-#if IS_ENABLED(CONFIG_AMD_SB_CIMX)
-	if (!acpi_is_wakeup_s3()) {
-		sb_After_Pci_Init();
-		sb_Mid_Post_Init();
-	} else {
-		sb_After_Pci_Restore_Init();
-	}
-#endif
-
-	if (!acpi_is_wakeup_s3()) {
-		/* Enable MMIO on AMD CPU Address Map Controller */
-		amd_initcpuio();
-
-		agesawrapper_amdinitmid();
-	}
-
-	printk(BIOS_DEBUG, "  ader - leaving domain_enable_resources.\n");
-#endif
-}
-
 static const char *domain_acpi_name(const struct device *dev)
 {
 	if (dev->path.type == DEVICE_PATH_DOMAIN)
@@ -786,7 +759,6 @@ struct chip_operations northbridge_amd_agesa_family14_ops = {
 static struct device_operations pci_domain_ops = {
 	.read_resources = domain_read_resources,
 	.set_resources = domain_set_resources,
-	.enable_resources = domain_enable_resources,
 	.init = DEVICE_NOOP,
 	.scan_bus = pci_domain_scan_bus,
 	.acpi_name = domain_acpi_name,
diff --git a/src/northbridge/amd/agesa/family15/Makefile.inc b/src/northbridge/amd/agesa/family15/Makefile.inc
index 25e3cc8f1f..3021ef48da 100644
--- a/src/northbridge/amd/agesa/family15/Makefile.inc
+++ b/src/northbridge/amd/agesa/family15/Makefile.inc
@@ -17,7 +17,5 @@ romstage-y += dimmSpd.c
 
 ramstage-y += northbridge.c
 
-ifneq ($(CONFIG_AGESA_LEGACY_WRAPPER), y)
 romstage-y += state_machine.c
 ramstage-y += state_machine.c
-endif
diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c
index 735e126bb9..2ef652d45d 100644
--- a/src/northbridge/amd/agesa/family15/northbridge.c
+++ b/src/northbridge/amd/agesa/family15/northbridge.c
@@ -36,7 +36,6 @@
 #include <Options.h>
 #include <Topology.h>
 
-#include <northbridge/amd/agesa/agesawrapper.h>
 #include <northbridge/amd/agesa/state_machine.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
 #include "sb_cimx.h"
@@ -633,23 +632,6 @@ static void domain_read_resources(device_t dev)
 	pci_domain_read_resources(dev);
 }
 
-static void domain_enable_resources(device_t dev)
-{
-#if IS_ENABLED(CONFIG_AGESA_LEGACY_WRAPPER)
-	/* Must be called after PCI enumeration and resource allocation */
-	printk(BIOS_DEBUG, "\nFam15 - %s: AmdInitMid.\n", __func__);
-
-#if IS_ENABLED(CONFIG_AMD_SB_CIMX)
-	sb_After_Pci_Init();
-#endif
-	/* Enable MMIO on AMD CPU Address Map Controller */
-	amd_initcpuio();
-
-	agesawrapper_amdinitmid();
-	printk(BIOS_DEBUG, "  Fam15 - leaving %s.\n", __func__);
-#endif
-}
-
 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
 struct hw_mem_hole_info {
 	unsigned hole_startk;
@@ -810,7 +792,6 @@ static void f15_pci_domain_scan_bus(device_t dev)
 static struct device_operations pci_domain_ops = {
 	.read_resources	  = domain_read_resources,
 	.set_resources	  = domain_set_resources,
-	.enable_resources = domain_enable_resources,
 	.init		  = DEVICE_NOOP,
 	.scan_bus	  = f15_pci_domain_scan_bus,
 	.ops_pci_bus	  = pci_bus_default_ops,
diff --git a/src/northbridge/amd/agesa/family15tn/Makefile.inc b/src/northbridge/amd/agesa/family15tn/Makefile.inc
index d6cbc1f120..9e9283c4be 100644
--- a/src/northbridge/amd/agesa/family15tn/Makefile.inc
+++ b/src/northbridge/amd/agesa/family15tn/Makefile.inc
@@ -18,7 +18,5 @@ romstage-y += dimmSpd.c
 ramstage-y += iommu.c
 ramstage-y += northbridge.c
 
-ifneq ($(CONFIG_AGESA_LEGACY_WRAPPER), y)
 romstage-y += state_machine.c
 ramstage-y += state_machine.c
-endif
diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c
index 675be14182..6face487f7 100644
--- a/src/northbridge/amd/agesa/family15tn/northbridge.c
+++ b/src/northbridge/amd/agesa/family15tn/northbridge.c
@@ -37,7 +37,6 @@
 #include <Options.h>
 #include <Topology.h>
 
-#include <northbridge/amd/agesa/agesawrapper.h>
 #include <northbridge/amd/agesa/state_machine.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
 
@@ -629,23 +628,6 @@ static void domain_read_resources(struct device *dev)
 	pci_domain_read_resources(dev);
 }
 
-static void domain_enable_resources(device_t dev)
-{
-#if IS_ENABLED(CONFIG_AGESA_LEGACY_WRAPPER)
-	if (acpi_is_wakeup_s3())
-		agesawrapper_fchs3laterestore();
-
-	/* Must be called after PCI enumeration and resource allocation */
-	if (!acpi_is_wakeup_s3()) {
-		/* Enable MMIO on AMD CPU Address Map Controller */
-		amd_initcpuio();
-
-		agesawrapper_amdinitmid();
-	}
-	printk(BIOS_DEBUG, "  ader - leaving %s.\n", __func__);
-#endif
-}
-
 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
 struct hw_mem_hole_info {
 	unsigned hole_startk;
@@ -800,7 +782,6 @@ static void domain_set_resources(struct device *dev)
 static struct device_operations pci_domain_ops = {
 	.read_resources	  = domain_read_resources,
 	.set_resources	  = domain_set_resources,
-	.enable_resources = domain_enable_resources,
 	.init		  = DEVICE_NOOP,
 	.scan_bus	  = pci_domain_scan_bus,
 	.ops_pci_bus	  = pci_bus_default_ops,
diff --git a/src/northbridge/amd/agesa/family16kb/Makefile.inc b/src/northbridge/amd/agesa/family16kb/Makefile.inc
index 25e3cc8f1f..3021ef48da 100644
--- a/src/northbridge/amd/agesa/family16kb/Makefile.inc
+++ b/src/northbridge/amd/agesa/family16kb/Makefile.inc
@@ -17,7 +17,5 @@ romstage-y += dimmSpd.c
 
 ramstage-y += northbridge.c
 
-ifneq ($(CONFIG_AGESA_LEGACY_WRAPPER), y)
 romstage-y += state_machine.c
 ramstage-y += state_machine.c
-endif
diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c
index 557c9c4bbd..98ed2b8913 100644
--- a/src/northbridge/amd/agesa/family16kb/northbridge.c
+++ b/src/northbridge/amd/agesa/family16kb/northbridge.c
@@ -36,7 +36,6 @@
 #include <Options.h>
 #include <Topology.h>
 
-#include <northbridge/amd/agesa/agesawrapper.h>
 #include <northbridge/amd/agesa/state_machine.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
 
@@ -644,23 +643,6 @@ static void domain_read_resources(device_t dev)
 	pci_domain_read_resources(dev);
 }
 
-static void domain_enable_resources(device_t dev)
-{
-#if IS_ENABLED(CONFIG_AGESA_LEGACY_WRAPPER)
-	if (acpi_is_wakeup_s3())
-		agesawrapper_fchs3laterestore();
-
-	/* Must be called after PCI enumeration and resource allocation */
-	if (!acpi_is_wakeup_s3()) {
-		/* Enable MMIO on AMD CPU Address Map Controller */
-		amd_initcpuio();
-
-		agesawrapper_amdinitmid();
-	}
-	printk(BIOS_DEBUG, "  ader - leaving domain_enable_resources.\n");
-#endif
-}
-
 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
 struct hw_mem_hole_info {
 	unsigned hole_startk;
@@ -816,7 +798,6 @@ static void domain_set_resources(device_t dev)
 static struct device_operations pci_domain_ops = {
 	.read_resources	  = domain_read_resources,
 	.set_resources	  = domain_set_resources,
-	.enable_resources = domain_enable_resources,
 	.init		  = DEVICE_NOOP,
 	.scan_bus	  = pci_domain_scan_bus,
 	.ops_pci_bus	  = pci_bus_default_ops,
diff --git a/src/northbridge/amd/agesa/state_machine.h b/src/northbridge/amd/agesa/state_machine.h
index f2551de5d9..81de242254 100644
--- a/src/northbridge/amd/agesa/state_machine.h
+++ b/src/northbridge/amd/agesa/state_machine.h
@@ -20,8 +20,7 @@
 #include <AGESA.h>
 #include <AMD.h>
 
-#define HAS_LEGACY_WRAPPER (IS_ENABLED(CONFIG_AGESA_LEGACY_WRAPPER) || \
-	IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER))
+#define HAS_LEGACY_WRAPPER IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)
 
 /* eventlog */
 const char *agesa_struct_name(int state);
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index c4cbd20f54..393eda0090 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -464,15 +464,14 @@ static void sb800_enable(device_t dev)
 	case (0x16 << 3) | 2: /* 0:16:2 EHCI-USB3 */
 		sb_config->USBMODE.UsbMode.Ehci3 = dev->enabled;
 
-#if 1 /* FIXME: IS_ENABLED(CONFIG_AGESA_LEGACY_WRAPPER) */
-		/* call the CIMX entry at the last sb800 device,
+		/* FIXME: Find better callsites for these.
+		 * call the CIMX entry at the last sb800 device,
 		 * so make sure the mainboard devicetree is complete
 		 */
 		if (!acpi_is_wakeup_s3())
 			sb_Before_Pci_Init();
 		else
 			sb_Before_Pci_Restore_Init();
-#endif
 		break;
 
 	default:
diff --git a/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h b/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h
index 6602c99d49..33a2139c6b 100644
--- a/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h
+++ b/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h
@@ -10,17 +10,10 @@
 
 #define AGESA_ENTRY_INIT_RESUME		IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
 
-#if IS_ENABLED(CONFIG_AGESA_LEGACY_WRAPPER)
-#define AGESA_ENTRY_INIT_ENV		TRUE
-#define AGESA_ENTRY_INIT_LATE_RESTORE	IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
-#endif
-
 #else
 
-#if !IS_ENABLED(CONFIG_AGESA_LEGACY_WRAPPER)
 #define AGESA_ENTRY_INIT_ENV		TRUE
 #define AGESA_ENTRY_INIT_LATE_RESTORE	IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
-#endif
 
 #define AGESA_ENTRY_INIT_MID		TRUE
 #define AGESA_ENTRY_INIT_LATE		TRUE