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| author | Subrata Banik <subrata.banik@intel.com> | 2021-07-23 15:30:30 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2021-07-24 11:14:08 +0000 |
| commit | 9bf4293c3ff5acab0542e73fc31d580446a73398 (patch) | |
| tree | 8ee7da9113a30d51cf670f8a9a0c5fdd0f588497 | |
| parent | 25429c06c3494f2f7b99670c4cee5b2775c52895 (diff) | |
include/cpu: Remove one space from bitfield macro definition
This change is to maintain parity with other macro declarations.
Change-Id: I67bf78884adf6bd7faa5bb3afa2c17262c89b770
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56559
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/include/cpu/x86/msr.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 4991e0311d..26f1dcb6cf 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -90,7 +90,7 @@ #define IA32_HWP_STATUS 0x777 #define IA32_PQR_ASSOC 0xc8f /* MSR bits 33:32 encode slot number 0-3 */ -#define IA32_PQR_ASSOC_MASK (1 << 0 | 1 << 1) +#define IA32_PQR_ASSOC_MASK (1 << 0 | 1 << 1) #define IA32_L3_MASK_1 0xc91 #define IA32_L3_MASK_2 0xc92 |