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authorIvy Jian <ivy.jian@quanta.corp-partner.google.com>2023-09-25 13:32:35 +0800
committerFelix Held <felix-coreboot@felixheld.de>2023-09-26 14:09:01 +0000
commit9bb02a8db1d200ad82f041aebf3e3ceef6ec2d74 (patch)
tree700ad93c7b85b7e268e5f6187c6d52f9adf7ae74
parente608a4f4fd2a615f49c3bdafc2b4781be3efb103 (diff)
mb/google/rex/var/rex0: Configure I2C5 timing
Configure I2C5 timing in devicetree to ensure I2C devices meet timing requirement. BUG=b:300177424 TEST=Build and check I2C devices timing meet spec. | | I2C5-Before | I2C5-After | |-------------|-------------|------------| | FSMB(KHz) | 445.400 | 343.638 | | TLOW(us) | 1.543 | 2.068 | | THIGH(us) | 0.475 | 0.604 | | THD:STA(us) | 0.603 | 0.711 | | TSU:STA(us) | 0.612 | 0.611 | | TSU:STO(us) | 0.605 | 0.611 | | TBUF(us) | >1.914 | >2.044 | Change-Id: I3bb678b66d55c6bfaff76e3e5500a2a3bc3a2c61 Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78111 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/google/rex/variants/rex0/overridetree.cb4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb
index d92dc24088..1d4ba630ca 100644
--- a/src/mainboard/google/rex/variants/rex0/overridetree.cb
+++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb
@@ -142,8 +142,8 @@ chip soc/intel/meteorlake
},
.i2c[5] = {
.speed = I2C_SPEED_FAST,
- .rise_time_ns = 900,
- .fall_time_ns = 400,
+ .rise_time_ns = 400,
+ .fall_time_ns = 280,
.data_hold_time_ns = 50,
},
}"