diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-22 18:37:32 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-08-03 05:32:20 +0000 |
| commit | 9addda3c410041ea93ae5587d17460da9a9c312f (patch) | |
| tree | 5579f274b2d7e801b819d5711ddbdf96414101c0 | |
| parent | c642a0d8942735b393040b877769f1d4a3a9ebe8 (diff) | |
nb/intel/ironlake: Add Generic Non-Core register definitions
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.
Change-Id: I4d878b5dbb5a5617143240b8f5bc5b6f5a754511
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
| -rw-r--r-- | src/northbridge/intel/ironlake/early_init.c | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/ironlake/ironlake.h | 4 | ||||
| -rw-r--r-- | src/northbridge/intel/ironlake/raminit.c | 6 |
3 files changed, 8 insertions, 4 deletions
diff --git a/src/northbridge/intel/ironlake/early_init.c b/src/northbridge/intel/ironlake/early_init.c index 24657d6616..fa89bd9e45 100644 --- a/src/northbridge/intel/ironlake/early_init.c +++ b/src/northbridge/intel/ironlake/early_init.c @@ -43,7 +43,7 @@ static void early_cpu_init(void) /* bit 0 = disable multicore, bit 1 = disable quadcore, bit 8 = disable hyperthreading. */ - pci_update_config32(QPI_NON_CORE, 0x80, 0xfffffefc, 0x10000); + pci_update_config32(QPI_NON_CORE, DESIRED_CORES, 0xfffffefc, 0x10000); u8 reg8; struct cpuid_result result; diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index 4f9db5b347..325de5b57f 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -52,6 +52,10 @@ */ #define QPI_NON_CORE PCI_DEV(QUICKPATH_BUS, 0, 0) +#define MAX_RTIDS 0x60 +#define DESIRED_CORES 0x80 +#define MIRROR_PORT_CTL 0xd0 + /* * SAD - System Address Decoder */ diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index 81a7727b86..dd1dbd001d 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -3955,8 +3955,8 @@ void raminit(const int s3resume, const u8 *spd_addrmap) pci_read_config32(QPI_LINK_0, QPI_DEF_RMT_VN_CREDITS); // !!!! pci_write_config32(QPI_LINK_0, QPI_DEF_RMT_VN_CREDITS, 0x64555); pci_read_config32(QPI_LINK_0, QPI_DEF_RMT_VN_CREDITS); // !!!! - pci_read_config32(QPI_NON_CORE, 0xd0); // !!!! - pci_write_config32(QPI_NON_CORE, 0xd0, 0x180); + pci_read_config32(QPI_NON_CORE, MIRROR_PORT_CTL); // !!!! + pci_write_config32(QPI_NON_CORE, MIRROR_PORT_CTL, 0x180); gav(MCHBAR32(0x1af0)); // !!!! gav(MCHBAR32(0x1af0)); // !!!! MCHBAR32(0x1af0) = 0x1f020003; @@ -4225,7 +4225,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap) MCHBAR8(0x2ca8) = MCHBAR8(0x2ca8); MCHBAR32_AND_OR(0x2c80, 0, 0x53688); // !!!! - pci_write_config32(QPI_NON_CORE, 0x60, 0x20220); + pci_write_config32(QPI_NON_CORE, MAX_RTIDS, 0x20220); MCHBAR16(0x2c20); // !!!! MCHBAR16(0x2c10); // !!!! MCHBAR16(0x2c00); // !!!! |