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authorRoger Wang <roger2.wang@lcfc.corp-partner.google.com>2024-06-13 10:40:29 +0800
committerFelix Held <felix-coreboot@felixheld.de>2024-06-18 21:52:54 +0000
commit9abc91cc451af09dc90505ae9be2d4f43f796373 (patch)
treed80551afc266509b715e2e1b04b8a7fea8b31234
parent2b8367ed4b1a1a92a4f56dabab284aaceb53f6c7 (diff)
mb/google/nissa/var/sundance: disable pcie port7
Disable pcie port7 to prevent s0ix issue when run the FAFT sleep test. BUG=b:328147465 TEST=Build and check S0ix function and verify FAFT sleep funciton. Change-Id: I53f704ed11a5c63b5c079c6e60ce2fa32bbd8b1a Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
-rw-r--r--src/mainboard/google/brya/variants/sundance/overridetree.cb1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/sundance/overridetree.cb b/src/mainboard/google/brya/variants/sundance/overridetree.cb
index 65d7e95cac..72cb317cb0 100644
--- a/src/mainboard/google/brya/variants/sundance/overridetree.cb
+++ b/src/mainboard/google/brya/variants/sundance/overridetree.cb
@@ -273,6 +273,7 @@ chip soc/intel/alderlake
device pci 00.0 on end
end
end
+ device ref pcie_rp7 off end
device ref pch_espi on
chip ec/google/chromeec
use conn0 as mux_conn[0]