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authorAngel Pons <th3fanbus@gmail.com>2021-03-01 21:16:49 +0100
committerPatrick Georgi <pgeorgi@google.com>2021-03-03 09:02:03 +0000
commit98521c51f473e3abc2bd0a7247e2a40c8d1e2711 (patch)
tree202b3940178907219c6ee60240ba5809942db956
parent68b447c2f8ed9b064ff3c915ae98ec8612d0ba3d (diff)
soc/intel: Retype `CnviBtAudioOffload` devicetree option
The `FORCE_ENABLE` and `FORCE_DISABLE` names do not match what FSP UPDs say, and can be confused with the `PchHdaTestPowerClockGating` UPD. Replace the enum with a bool, and drop the confusing names. Note that the enum for Ice Lake was incorrect, but no mainboards used the option. Change-Id: I2c9b4c6a2f210ffca946ca196299fa672a06ccc7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51154 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/google/volteer/variants/baseboard/devicetree.cb2
-rw-r--r--src/soc/intel/alderlake/chip.h5
-rw-r--r--src/soc/intel/elkhartlake/chip.h5
-rw-r--r--src/soc/intel/icelake/chip.h6
-rw-r--r--src/soc/intel/jasperlake/chip.h5
-rw-r--r--src/soc/intel/tigerlake/chip.h5
6 files changed, 6 insertions, 22 deletions
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
index 6a826c0bd2..825005e829 100644
--- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -289,7 +289,7 @@ chip soc/intel/tigerlake
register "tcc_offset" = "10" # TCC of 90
- register "CnviBtAudioOffload" = "FORCE_ENABLE"
+ register "CnviBtAudioOffload" = "true"
# Intel Common SoC Config
#+-------------------+---------------------------+
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 13e77cf534..fa9fce2998 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -207,10 +207,7 @@ struct soc_intel_alderlake_config {
uint8_t pch_isclk;
/* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */
- enum {
- FORCE_DISABLE,
- FORCE_ENABLE,
- } CnviBtAudioOffload;
+ bool CnviBtAudioOffload;
/*
* IOM Port Config
diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h
index 1d97b36084..c3a7ac19d6 100644
--- a/src/soc/intel/elkhartlake/chip.h
+++ b/src/soc/intel/elkhartlake/chip.h
@@ -196,10 +196,7 @@ struct soc_intel_elkhartlake_config {
unsigned int sdcard_cd_gpio;
/* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */
- enum {
- FORCE_DISABLE,
- FORCE_ENABLE,
- } CnviBtAudioOffload;
+ bool CnviBtAudioOffload;
/* Tcss */
uint8_t TcssXhciEn;
diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h
index 64bc70ba53..b878fd6edb 100644
--- a/src/soc/intel/icelake/chip.h
+++ b/src/soc/intel/icelake/chip.h
@@ -184,11 +184,7 @@ struct soc_intel_icelake_config {
uint8_t pch_isclk;
/* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */
- enum {
- PLATFORM_POR,
- FORCE_ENABLE,
- FORCE_DISABLE,
- } CnviBtAudioOffload;
+ bool CnviBtAudioOffload;
/*
* Override GPIO PM configuration:
diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h
index 6e52efded3..c25ccbf6fe 100644
--- a/src/soc/intel/jasperlake/chip.h
+++ b/src/soc/intel/jasperlake/chip.h
@@ -199,10 +199,7 @@ struct soc_intel_jasperlake_config {
uint8_t pch_isclk;
/* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */
- enum {
- FORCE_DISABLE,
- FORCE_ENABLE,
- } CnviBtAudioOffload;
+ bool CnviBtAudioOffload;
/* Tcss */
uint8_t TcssXhciEn;
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index cccf80476e..76a24807fc 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -317,10 +317,7 @@ struct soc_intel_tigerlake_config {
} debug_interface_flag;
/* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */
- enum {
- FORCE_DISABLE,
- FORCE_ENABLE,
- } CnviBtAudioOffload;
+ bool CnviBtAudioOffload;
/* TCSS USB */
uint8_t TcssXhciEn;