diff options
| author | Mike Banon <mikebdp2@gmail.com> | 2019-01-15 03:03:16 +0300 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2019-01-16 00:20:29 +0000 |
| commit | 90af720d4e7e6f6d8e3f9fe55e9de0b59abb403d (patch) | |
| tree | fad20d0c0988226bc013a16bc19cc2c1df9334a7 | |
| parent | 1e2676bf1bd0c2c0083239f29164048eb7645496 (diff) | |
drivers/spi/sst.c: Add three remaining SST25*F080 chips
Required for ACPI S3 suspend support at some motherboards.
Synchronizing with flashchips.c/h flashrom source code.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: Idc63665937ab1bfdf15c4054001daa288bfdd47b
Reviewed-on: https://review.coreboot.org/c/30927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
| -rw-r--r-- | src/drivers/spi/sst.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/drivers/spi/sst.c b/src/drivers/spi/sst.c index 559969a0ba..63fae95636 100644 --- a/src/drivers/spi/sst.c +++ b/src/drivers/spi/sst.c @@ -78,6 +78,11 @@ static const struct sst_spi_flash_params sst_spi_flash_table[] = { .name = "SST25VF080B", .ops = &spi_flash_ops_write_ai, },{ + .idcode1 = 0x80, + .nr_sectors = 256, + .name = "SST25VF080", + .ops = &spi_flash_ops_write_ai, + },{ .idcode1 = 0x41, .nr_sectors = 512, .name = "SST25VF016B", @@ -112,6 +117,16 @@ static const struct sst_spi_flash_params sst_spi_flash_table[] = { .nr_sectors = 128, .name = "SST25WF040", .ops = &spi_flash_ops_write_ai, + },{ + .idcode1 = 0x05, + .nr_sectors = 256, + .name = "SST25WF080", + .ops = &spi_flash_ops_write_ai, + },{ + .idcode1 = 0x14, + .nr_sectors = 256, + .name = "SST25WF080B", + .ops = &spi_flash_ops_write_ai, }, }; |