diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2019-12-28 18:57:06 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2019-12-29 12:20:16 +0000 |
| commit | 8fa02a8ef91a2bc5c45bed7c42c6e6ecef126ea3 (patch) | |
| tree | 9f12d194afe602b43ae76c00d29c6dba8714e68a | |
| parent | bc3668a4687f68fb1bfb39ec89fa863879fed2ac (diff) | |
nb/intel/sandybridge: simplify ME lock and memory enable bit write
Timeless build results in identical image for X230.
Change-Id: I36842ebd4917e96aa8aec87ba13d27bd4bf44b76
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_common.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 8f58dcba83..b12ea25f25 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -608,9 +608,8 @@ void dram_memorymap(ramctr_timing * ctrl, int me_uma_size) reg = pci_read_config32(PCI_DEV(0, 0, 0), MEMASK); val = (0x80000 - me_uma_size) & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); - reg = (reg & ~0x400) | (1 << 10); // set lockbit on ME mem - - reg = (reg & ~0x800) | (1 << 11); // set ME memory enable + reg = reg | (1 << 10); // set lockbit on ME mem + reg = reg | (1 << 11); // set ME memory enable printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MEMASK, reg); pci_write_config32(PCI_DEV(0, 0, 0), MEMASK, reg); } |