AMD binaryPI: Declare IOAPIC IDs

There is no longer a relation between MAX_CPUS and IOAPIC IDs,
start the cleanup with new declarations.

Change-Id: I65888550e359e55402d99e8816ece2061cfcccbc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

5 files changed, 22 insertions, 8 deletions

diff --git a/src/northbridge/amd/pi/00730F01/acpi_tables.c b/src/northbridge/amd/pi/00730F01/acpi_tables.c
index 1cf7e74722..bb510cd72c 100644
--- a/src/northbridge/amd/pi/00730F01/acpi_tables.c
+++ b/src/northbridge/amd/pi/00730F01/acpi_tables.c
@@ -3,6 +3,7 @@
 #include <acpi/acpi.h>
 #include <arch/ioapic.h>
 #include <northbridge/amd/nb_common.h>
+#include <southbridge/amd/pi/hudson/ioapic.h>
 
 unsigned long acpi_fill_madt(unsigned long current)
 {
@@ -10,11 +11,11 @@ unsigned long acpi_fill_madt(unsigned long current)
 	current = acpi_create_madt_lapics_with_nmis(current);
 
 	/* Write SB800 IOAPIC, only one */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, CONFIG_MAX_CPUS,
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, FCH_IOAPIC_ID,
 					   IO_APIC_ADDR, 0);
 
 	/* TODO: Remove the hardcode */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, CONFIG_MAX_CPUS + 1,
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, GNB_IOAPIC_ID,
 					   IO_APIC2_ADDR, 24);
 
 	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c
index dab0e72d50..644e2d5e3d 100644
--- a/src/northbridge/amd/pi/00730F01/northbridge.c
+++ b/src/northbridge/amd/pi/00730F01/northbridge.c
@@ -23,6 +23,7 @@
 #include <northbridge/amd/nb_common.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
 #include <southbridge/amd/pi/hudson/pci_devs.h>
+#include <southbridge/amd/pi/hudson/ioapic.h>
 #include <amdblocks/cpu.h>
 
 #define MAX_NODE_NUMS MAX_NODES
@@ -221,7 +222,7 @@ static void nb_set_resources(struct device *dev)
 
 static void northbridge_init(struct device *dev)
 {
-	setup_ioapic((u8 *)IO_APIC2_ADDR, CONFIG_MAX_CPUS + 1);
+	setup_ioapic((u8 *)IO_APIC2_ADDR, GNB_IOAPIC_ID);
 }
 
 static unsigned long acpi_fill_hest(acpi_hest_t *hest)
@@ -253,7 +254,7 @@ unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current)
 	ivhd_ioapic->dte_setting = IVHD_DTE_LINT_1_PASS | IVHD_DTE_LINT_0_PASS |
 				   IVHD_DTE_SYS_MGT_NO_TRANS | IVHD_DTE_NMI_PASS |
 				   IVHD_DTE_EXT_INT_PASS | IVHD_DTE_INIT_PASS;
-	ivhd_ioapic->handle = CONFIG_MAX_CPUS; /* FCH IOAPIC ID */
+	ivhd_ioapic->handle = FCH_IOAPIC_ID;
 	ivhd_ioapic->source_dev_id = PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC);
 	ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC;
 	current += sizeof(ivrs_ivhd_special_t);
@@ -263,7 +264,7 @@ unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current)
 	ivhd_ioapic->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV;
 	ivhd_ioapic->reserved = 0x0000;
 	ivhd_ioapic->dte_setting = 0x00;
-	ivhd_ioapic->handle = CONFIG_MAX_CPUS + 1; /* GNB IOAPIC ID */
+	ivhd_ioapic->handle = GNB_IOAPIC_ID;
 	ivhd_ioapic->source_dev_id = PCI_DEVFN(0, 1);
 	ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC;
 	current += sizeof(ivrs_ivhd_special_t);
diff --git a/src/northbridge/amd/pi/00730F01/state_machine.c b/src/northbridge/amd/pi/00730F01/state_machine.c
index ba34dabde9..0693a5d93c 100644
--- a/src/northbridge/amd/pi/00730F01/state_machine.c
+++ b/src/northbridge/amd/pi/00730F01/state_machine.c
@@ -9,6 +9,7 @@
 #include <northbridge/amd/agesa/state_machine.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
 #include <northbridge/amd/nb_common.h>
+#include <southbridge/amd/pi/hudson/ioapic.h>
 
 void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
 {
@@ -64,8 +65,8 @@ void platform_BeforeInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late)
 		 * when IOMMU build config is enabled otherwise AGESA will skip
 		 * it during IOMMU init and IVRS generation.
 		 */
-		Late->GnbLateConfiguration.GnbIoapicId = CONFIG_MAX_CPUS + 1;
-		Late->GnbLateConfiguration.FchIoapicId = CONFIG_MAX_CPUS;
+		Late->GnbLateConfiguration.GnbIoapicId = GNB_IOAPIC_ID;
+		Late->GnbLateConfiguration.FchIoapicId = FCH_IOAPIC_ID;
 	}
 
 	/* Code for creating CDIT requires hop count table. If it is not
diff --git a/src/southbridge/amd/pi/hudson/ioapic.h b/src/southbridge/amd/pi/hudson/ioapic.h
new file mode 100644
index 0000000000..757e5c83d5
--- /dev/null
+++ b/src/southbridge/amd/pi/hudson/ioapic.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_BLOCK_IOAPIC_H
+#define AMD_BLOCK_IOAPIC_H
+
+/* Since the old APIC bus isn't used any more, the IOAPIC IDs could be < CONFIG_MAX_CPUS */
+#define FCH_IOAPIC_ID		(CONFIG_MAX_CPUS)
+#define GNB_IOAPIC_ID		(CONFIG_MAX_CPUS + 1)
+
+#endif /* AMD_BLOCK_IOAPIC_H */
diff --git a/src/southbridge/amd/pi/hudson/sm.c b/src/southbridge/amd/pi/hudson/sm.c
index 79d1005997..c40bf5e1c9 100644
--- a/src/southbridge/amd/pi/hudson/sm.c
+++ b/src/southbridge/amd/pi/hudson/sm.c
@@ -5,6 +5,7 @@
 #include <device/pci_ids.h>
 #include <device/smbus.h>
 #include <arch/ioapic.h>
+#include <southbridge/amd/pi/hudson/ioapic.h>
 
 #include "hudson.h"
 #include "smbus.c"
@@ -21,7 +22,7 @@
 
 static void sm_init(struct device *dev)
 {
-	setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS);
+	setup_ioapic(VIO_APIC_VADDR, FCH_IOAPIC_ID);
 }
 
 static int lsmbus_recv_byte(struct device *dev)